Intel SL3QA - Pentium III 550 MHz Processor Specification page 77

Errata
• The example workaround circuit assumes that the PWRGD inputs into the
processors are open collector. Tying the PWRGD inputs together in a Wired-AND
fashion allows each processor to receive PWRGD at the same time but at the
latter of the 2 separate PWRGD assertions. If separation of the PWRGD inputs to
each processor is required, extra circuitry will be required.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E79. Processor Might not Exit Sleep State Properly Upon De-assertion of
CPUSLP# Signal
Problem: If the processor enters a sleep state upon assertion of CPUSLP# signal, and if the
core to system bus multiplier is an odd bus fraction, then the processor may not
resume from the CPU sleep state upon the de-assertion of CPUSLP# signal.
Implication: This erratum may result in a system hang during a resume from CPU sleep state.
Workaround: It is possible to workaround this in BIOS by not asserting CPUSLP# for power
management purposes
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E80. The Instruction Fetch Unit (IFU) May Fetch Instructions Based Upon
Stale CR3 Data after a Write to CR3 Register
Problem: Under a complex set of conditions, there exists a one-clock window following a write
to the CR3 register wherein it is possible for the iTLB fill buffer to obtain a stale page
translation based on the stale CR3 data. This stale translation will persist until the
next write to the CR3 register, the next page fault or execution of a certain class of
instructions including CPUID or IRETD with privilege level change.
Implication: The wrong page translation could be used leading to erroneous software behavior.
Workaround: Operating systems that are potentially affected can add a second write to the
CR3 register.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E81. Under Some Complex Conditions, the Instructions in the Shadow of a
JMP FAR may be Unintentionally Executed and Retired
Problem: If all of the following events happen in sequence it is possible for the system or
application to hang or to execute with incorrect data.
1. The execution of an instruction, with an OPCODE that requires the processor to
stall the issue of micro-instructions in the flow from the microcode sequence logic
block to the instruction decode block. (a StallMS condition)
2. Less than 63 (39 for Pre-CPUID 0x6BX) micro-instructions later, the execution of a
mispredictable branch instruction. (Jcc, LOOPcc, RET Near, CALL Near Indirect,
JMP ECX=0, or JMP Near Indirect)
Specification Update 77