Intel SL3QA - Pentium III 550 MHz Processor Specification page 66

Under a complex set of internal and external conditions involving illegal instructions,
a deadlock may occur within the processor.
deadlock involve:
1. Execution of the illegal instruction.
2. Two-page table walks occur within a narrow timing window coincident with the
illegal instruction.
Implication: The illegal instructions involved in this erratum are unusual and invalid byte
combinations that are not useful to application software or operating systems. These
combinations are not normally generated in the course of software programming, nor
are such sequences known by Intel to be generated in commercially available
software and tools. Development tools (compilers, assemblers) do not generate this
type of code sequence, and will normally flag such a sequence as an error. If this
erratum occurs, the processor deadlock condition will occur and result in a system
hang. Code execution cannot continue without a system RESET.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E58. MASKMOVQ Instruction Interaction with String Operation May Cause
Deadlock
Problem: Under the following scenario, combined with a specific alignment of internal events,
the processor may enter a deadlock condition:
1. A store operation completes, leaving a write-combining (WC) buffer partially
filled.
2. The target of a subsequent MASKMOVQ instruction is split across a cache line.
3. The data in (2) above results in a hit to the data in the WC buffer in (1).
Implication: If this erratum occurs, the processor deadlock condition will occur and result in a
system hang. Code execution cannot continue without a system RESET.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E59. MOVD, CVTSI2SS, or PINSRW Following Zeroing Instruction Can
Cause Incorrect Result
Problem: An incorrect result may be calculated after the following circumstances occur:
1. A register has been zeroed with either a SUB reg, reg instruction, or an XOR reg,
reg instruction.
2. A value is moved with sign extension into the same register's lower 16 bits; or a
signed integer multiply is performed to the same register's lower 16 bits.
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The necessary conditions for the
Specification Update
Errata