Intel SL3QA - Pentium III 550 MHz Processor Specification page 46

after either a CALL which results in a fault or a software interrupt, the LBER and LBR
will be updated to the same value, when the LBER should not have been updated.
Implication: The LBER and LBR registers are used only for debugging purposes. When this
erratum occurs, the LBER will not contain reliable address information. The value of
LBER should be used with caution when debugging branching code; if the values in
the LBR and LBER are the same, then the LBER value is incorrect. Also, the value in
the LBER should not be relied upon after a BINIT# event.
Workaround: None identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E15. BTMs May Be
Replacement
Problem: When Branch Trace Messages (BTMs) are enabled and such a message is generated,
the BTM may be corrupted when issued to the bus by the L1 cache if a new line of
data is brought into the L1 data cache simultaneously. Though the new line being
stored in the L1 cache is stored correctly, and no corruption occurs in the data, the
information in the BTM may be incorrect due to the internal collision of the data line
and the BTM.
Implication: Although BTMs may not be entirely reliable due to this erratum, the conditions
necessary for this boundary condition to occur have only been exhibited during
focused simulation testing. Intel has currently not observed this erratum in a system
level validation environment.
Workaround: None identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E16. EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
Problem: This erratum may occur when the Pentium III processor executes one of the following
read-modify-write arithmetic instructions and a page fault occurs during the store of
the memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT,
OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD. In this case,
the EFLAGS value pushed onto the stack of the page fault handler may reflect the
status of the register after the instruction would have completed execution rather
than before it. The following conditions are required for the store to generate a page
fault and call the operating system page fault handler:
1. The store address entry must be evicted from the DTLB by speculative loads from
other instructions that hit the same way of the DTLB before the store has
completed. DTLB eviction requires at least three-load operations that have linear
address bits 15:12 equal to each other and address bits 31:16 different from
each other in close physical proximity to the arithmetic operation.
2. The page table entry for the store address must have its permissions tightened
during the very small window of time between the DTLB eviction and execution of
46
Corrupted During Simultaneous L1
Errata
Cache Line
Specification Update