Sun Microsystems Sun Blade 1000 Service Manual page 99

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diag-level Variable Set to min (Single CPU) (Continued) (3 of 8)
CODE EXAMPLE 3-4
{0}Test walking 1 through the register
{0}Testing D-TSB
{0}Test walking 1 through the register
{0}Testing D-TLB Tag Access
{0}Test walking 1 through the register
{0}Testing Virtual Watchpoint
{0}Test walking 1 through the register
{0}Testing Physical Watchpoint
{0}Test walking 1 through the register
{0}* 4M DTLB RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 8K DTLB RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 4M DTLB TAG
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 8K DTLB TAG
{0}Test address up
{0}Test address down
{0}Test address line transitions
{0}* 4M ITLB RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 8K ITLB RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 4M ITLB TAG
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}* 8K ITLB TAG
{0}Test address up
{0}Test address down
{0}Test address line transitions
{0}* IMMU Init
{0}* DMMU Init
{0}Mapping done. MMU enabled
{0}* Memory address selection Initial area
{0}* E-Cache Global Vars Init
Chapter 3 Power On Self-Test
3-45

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