Sun Microsystems Sun Blade 1000 Service Manual page 93

diag-level Variable Set to min (2-Way CPU) (9 of 12)
CODE EXAMPLE 3-3
{1}Test cell disturbance
{1}* P-Cache Init
{1}* FPU Registers
{1}Test walking 1/0 FPU registers
{0}Test register addressing
{0}* FSR
{0}Test walking 1 FSR register
{0}* Ecache RAM
{1}Test register addressing
{0}Test address up
{1}* FSR
{1}Test walking 1 FSR register
{1}* Ecache RAM
{1}Test address up
{0}Test address down
{1}Test address down
{0}Test cell disturbance
{1}Test cell disturbance
{0}* Ecache Init
{1}* Ecache Init
{0}* Correctable Ecache ECC Test
{1}* Correctable Ecache ECC Test
{0}* Uncorrectable Ecache ECC Test
{1}* Uncorrectable Ecache ECC Test
{0}* Correctable SW Ecache ECC Test
{1}* Correctable SW Ecache ECC Test
{0}* Uncorrectable SW Ecache ECC Test
{1}* Uncorrectable SW Ecache ECC Test
{0}* Correctable System ECC Test
{1}* Correctable System ECC Test
{0}* Uncorrectable System ECC Test
{1}* Uncorrectable System ECC Test
{0}* Memory address selection All Banks
{1}* Memory address selection All Banks
{0}* Safari registers
{0}Safari ID reg fc000000.0011a953
{0}* Map PCI A space
{1}* Map PCI B space
{0}* Schizo reg test
{1}* Schizo reg test
{0}PBM A registers
{1}PBM B registers
{0}Iommu A registers
{1}Iommu B registers
Chapter 3 Power On Self-Test 3-39