Sun Microsystems Sun Blade 1000 Service Manual page 297

Access to the boot PROM through the BBC is optimized for 16-byte master accesses
performed by the CPU on the BootBus.
BBC is also a slave on EBus and all its internal registers are accessible through the
PCIO-2. Thus software drivers running on Solaris software can access the necessary
®
resources such as the Energy Star software and the thermal management driver.
BBC also supports many other functions that are briefly introduced in the following
subsections.
Reset Controller
The BBC is the reset controller in the Sun Blade 1000 and Sun Blade 2000
workstation. The controller receives the reset source lines and is responsible for
generating the reset signals for the CPU module and the overall system. The external
sources for reset include the power up reset from the power supply, the reset buttons
on the motherboard, the SuperI/O watchdog timer, and fatal error conditions.
The reset controller also includes registers that a processor uses to generate an
external reset to itself or another processor.
JTAG Controller
BBC is the host for the JTAG+ controller that includes a programmable master tap
controller. This allows processors to access the JTAG scan rings in the system by
simply executing programmed I/O operations to the BBC master tap controller
registers. The processor(s) can access the internal scan chain of all the ASICs and
perform different levels of testing (boundary scan, internal scan for ATPG, RAM
tests, and BIST if available).
The JTAG+ controller allows for an external JTAG master to be connected to the
motherboard for controlling all scan rings including the processor(s) scan ring(s) and
the BBC internal scan ring.
I2C Buses
The BBC supports five master I2C buses and a single multi-master I2C bus.
Small I2C serial EEPROMs make it possible to identify pluggable modules that
cannot be identified easily through their regular data path. The DIMMs include an
I2C serial EEPROM that contains information relative to the size and the speed of
the DRAM. The CPU modules include an I2C EEPROM which indicates the size of
the second level cache and the speed of the processor.
Appendix C Functional Description C-25