Sun Microsystems Sun Blade 1000 Service Manual page 81

diag-level Variable Set to max (single CPU) (6 of 9)
CODE EXAMPLE 3-2
{0}* P-Cache RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache TAGS
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache SnoopTags
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache Status Data
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache Init
{0}* FPU Registers
{0}Test walking 1/0 FPU registers
{0}Test register addressing
{0}* FSR
{0}Test walking 1 FSR register
{0}* Ecache RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* Ecache Init
{0}* Correctable Ecache ECC Test
{0}* Uncorrectable Ecache ECC Test
{0}* Correctable SW Ecache ECC Test
{0}* Uncorrectable SW Ecache ECC Test
{0}* Correctable System ECC Test
{0}* Uncorrectable System ECC Test
{0}* Memory address selection All Banks
Chapter 3 Power On Self-Test 3-27