Sun Microsystems Sun Blade 1000 Service Manual page 70

CODE EXAMPLE 3-1
{0}Test address line transitions
{0}* P-Cache TAGS
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache SnoopTags
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache Status Data
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* P-Cache Init
{0}* FPU Registers
{0}Test walking 1/0 FPU registers
3-16 Sun Blade 1000 and Sun Blade 2000 Service Manual • January 2002
diag-level Variable Set to max (2-Way CPU) (10 of 15)
{1}Test address line transitions
{1}* W-Cache Init
{1}* P-Cache RAM
{1}Test address up
{1}Test address down
{1}Test cell disturbance
{1}Test data reliability
{1}Test address line transitions
{1}* P-Cache TAGS
{1}Test address up
{1}Test address down
{1}Test cell disturbance
{1}Test data reliability
{1}Test address line transitions
{1}* P-Cache SnoopTags
{1}Test address up
{1}Test address down
{1}Test cell disturbance
{1}Test data reliability
{1}Test address line transitions
{1}* P-Cache Status Data
{1}Test address up
{1}Test address down