Sun Microsystems Sun Blade 1000 Service Manual page 295

I/O interrupts are issued on separate lines by the various on-board devices, the PCI
cards, and UPA cards. The interrupts are routed to an interrupt concentrator: the I-
chip that encodes the interrupts and delivers them to the SBC. The SBC issues a
single Sun CrossBar Interconnect interrupt transaction for each active interrupt.
The following diagram depicts the overall interrupt organization in the Sun Blade
1000 and Sun Blade 2000 workstation:
4
P
C
I
S
l
o
t
0
FIGURE C-8
C.1.6 BootBus
The CPU module supports an alternate 8-bit bus (the BootBus) used after a reset to
fetch the first instruction they execute.
The address space of the BootBus corresponds to the boot PROM addressing space
as defined by the Sun4u/Sun5 architecture. The CPU issues its SPARC V9
RED_MODE trap vectors from this address space.
The following block diagram shows how the CPUs access the boot PROM through
the BootBus, the BBC, and EBus:
CPU
SBC
6
I chip
4 4 4 2
P P
PCIO 876
C C
-2
I I
S S
l l
o o
t t
1 2
Sun Blade 1000 and Sun Blade 2000
CPU
Sun CrossBar
Interconnect
1 1 1
4
14
E
ISP U U
EBus
P
P P
2200
C
A A
Dev
I
S S
S
l l
l
o o
o
t t
t
0 1
0
Interrupt Block Diagram
Appendix C Functional Description C-23