diag-level Variable Set to max (single CPU) (4 of 9)
CODE EXAMPLE 3-2
{0}Test address up
{0}Test address down
{0}Test address line transitions
{0}* IMMU Init
{0}* DMMU Init
{0}Mapping done. MMU enabled
{0}* Memory address selection Initial area
{0}* Memory marching Initial area
{0}* E-Cache Global Vars Init
{0}* E-Cache Quick Verification
{0}* Ecache TAGS
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* Ecache Address Line
{0}* Partial Ecache Init
{0}* BBC E-Star Registers
{0}* I-Cache RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* I-Cache TAGS
{0}Testing I-Cache Tag
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}Testing I-Cache Micro Tag
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* I-Cache Snoop Tags
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{0}Test data reliability
{0}Test address line transitions
{0}* I-Cache Init
Chapter 3 Power On Self-Test
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