diag-level Variable Set to max (2-Way CPU) (5 of 15)
CODE EXAMPLE 3-1
{0}Test address line transitions
{1}Test address line transitions
{0}* 4M ITLB RAM
{0}Test address up
{0}Test address down
{0}Test cell disturbance
{1}* 4M ITLB RAM
{0}Test data reliability
{1}Test address up
{1}Test address down
{0}Test address line transitions
{1}Test cell disturbance
{0}* 8K ITLB RAM
{1}Test data reliability
{0}Test address up
{1}Test address line transitions
{0}Test address down
{1}* 8K ITLB RAM
{1}Test address up
{0}Test cell disturbance
{1}Test address down
{1}Test cell disturbance
{0}Test data reliability
{1}Test data reliability
{0}Test address line transitions
{0}* 4M ITLB TAG
{1}Test address line transitions
{0}Test address up
{0}Test address down
{1}* 4M ITLB TAG
{0}Test cell disturbance
{1}Test address up
{0}Test data reliability
{1}Test address down
{1}Test cell disturbance
{0}Test address line transitions
{1}Test data reliability
{0}* 8K ITLB TAG
{0}Test address up
{1}Test address line transitions
{0}Test address down
{1}* 8K ITLB TAG
{1}Test address up
Chapter 3 Power On Self-Test
3-11