Sun Microsystems Sun Blade 1000 Service Manual page 282

The main memory data bus is 576 bits wide which corresponds to an external cache
block of 64 bytes. The systems main memory delivers an entire block of information
on external cache in a single memory bus cycle. This delivery method provides up to
2.4 GBps of sustainable bandwidth.
The main memory is implemented with x144 DIMMs, also referred to as NG-DIMMs
(next generation dual-in line memory modules). The system supports up to eight
installed NG-DIMMs.
Note – The memory bus is clocked at half the system frequency through a clock
connected directly to the CPU module.
The DIMMs also support a SEEPROM for identifying and configuring subsystem
memory.
The CPU module memory controller performs reads and writes in blocks of 64 bytes.
On noncacheable reads the extraneous data is dropped. On noncacheable write, the
processor must perform a read-modify-write. The memory space is cached.
The memory subsystem supports logical interleaving by 1 (no interleaving), 2, and 4.
The unit of interleaving is a logical bank. A group of four DIMMs corresponds to
two logical banks for interleaving purposes. The interleaving is based on multiples
of 64 bytes. Main memory interleaving is described in more details in Section C.1.3.5,
"System Memory Interleaving" on page C-14.
C-10 Sun Blade 1000 and Sun Blade 2000 Service Manual • January 2002