Sun Microsystems Ultra 20 User Manual page 125

BIOS Port 80 POST Codes (Continued)
TABLE C-1
Post Code Description
29h 1. Program CPU internal MTRR (P6 and PII) for 0-640K memory
address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example:
onboard IDE controller.
4. Measure CPU speed.
2Ah Reserved.
2Bh Invoke video BIOS.
2Ch Reserved.
2Dh 1. Initialize double-byte language font (optional).
2. Put information onscreen display, including award title, CPU
type, CPU speed, and full screen logo.
2Eh Reserved.
2Fh Reserved.
30h Reserved.
31h Reserved.
32h Reserved.
33h Reset keyboard if Early_Reset_KB is defined–e.g. Winbond 977
series Super I/O chips. See also POST 63h.
34h Reserved.
35h Test DMA Channel 0.
36h Reserved.
37h Test DMA Channel 1.
38h Reserved.
39h Test DMA page registers.
3Ah Reserved.
3Bh Reserved.
3Ch Test 8254.
3Dh Reserved.
3Eh Test 8259 interrupt mask bits for channel 1.
3Fh Reserved.
40h Test 8259 interrupt mask bits for channel 2.
41h Reserved.
Appendix C BIOS POST Codes C-5