HP E1563A User Manual page 128

Sample Count Low
Word Register
base + 3A 15 14
16
Write C15 C14
Read C15 C14
Trigger Source/
Control Register
base + 3C 15 14
16
Write* CMP4 CMP3 CMP2 CMP1
Read** CMP4 CMP3 CMP2 CMP1
Trigger Source/Control register bits defined:
bits 0-2 TTL_n
bit 3 IN/OUT
bit 4 EN_TTL
bit 5 SLAVE
bit 6 MASTER
bit 7 SOFT TRIG
bit 8 POS_NEG
bit 9 EX_TRIG
bits 10-11 SLAVING_PAIR
bits 12-15 CMP1-4
128 HP E1563A and E1564A Register-Based Programming
Register containing the low word (2 bytes) for the sample count.
This register and the high byte in register 38
be set by the SAMPle:COUNt command in Chapter 3. Chapter 2,
Figure 2-3 shows the relationship of the sample count and the pre-
trigger count.
13 12 11 10
C13 C12 C11 C10
C13 C12 C11 C10
This register provides the bits that control the trigger system.
13 12 11 10
SLAVING
PAIR
SLAVING
PAIR
*WRITE BITS (Trigger Source Register) and
**READ BITS (Trigger Control Register)
000 = TTLT0, 001 = TTLT1, 010 = TTLT2, ... , 011 = TTLT6, 111 = TTLT7.
TTLTn line is: 0 = IN, 1 = OUT.
0 = disable TTLTn, 1 = enable TTLTn
0 = not a slave module, 1 = slave module.
0 = not a master module, 1 = master module.
software trigger: 0 = IMMediate disabled, 1 = IMMediate enabled.
trigger slope: 0 = NEG, 1 = POS.
0 = EXTernal trigger disabled, 1 = EXTernal trigger enabled and must be
input on the "Trig" pin on the front panel D-subminiature connector.
00 = MASTer0/SLAVe0; 01 = MASTer2/SLAVe2;
10 = MASTer4/SLAVe4; 11 = MASTer6/SLAVe6
0 = INTn disabled, 1 = INTn enabled; Example: a "1" in CMP2 means the
level set in the Trigger/Interrupt Level Channel 2 Register will be used as the
INTernal trigger source.
NOTE
See the section titled "Master-Slave Operation" at the end of this appendix
for more information on register programming the digitizer in a master-slave
configuration. This uses bits 5, 6, 10 and 11 of the above register.
9 8 7 6
C9 C8 C7 C6
C9 C8 C7 C6
9 8 7 6
EX_ POS_ SOFT MAS-
TER
TRIG NEG TRIG
EX_ POS_ SOFT
MAS-
TER
TRIG NEG TRIG
hold a value that can
16
5 4 3 2
C5 C4 C3 C2
C5 C4 C3 C2
5 4 3 2
SLAVE EN_ IN/ TTL_3 TTL_1 TTL_0
TTL OUT
EN_ IN/ TTL_3 TTL_1 TTL_0
SLAVE
TTL OUT
Appendix B
1 0
C1 C0
C1 C0
1 0