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bit 12
bit 13
MOT-INTEL
bit 14
bit 15
Reading the Register
A24 Offset Register
base + 06
15
14
16
Write*
A23
A22
Read**
A24 Offset register bits defined:
bits 8-15
A16-A23
bits 8-15
A24
Offset
Cache FIFO High
Word Register
Appendix B
**READ BITS (Status/Control Register)
A24
"1" sets A24 space as all FIFO, "0" sets A24 space as broken up.
"1" = Motorola big endian byte swapping, "0" = Intel little endian byte swapping.
M
MODID bit; if the bit is "0", module has been selected.
A
A24/A32 enable; "1" = A32 decoding enabled, "0" = A24 decoding enabled.
•
Via Command Module PEEK command: DIAG:PEEK? 2083332,16
(2083328 = base with logical address 40 + 04 offset; see Figure B-2)
•
Via Digitizer Module PEEK command: DIAG:PEEK? 2
(2 signifies the third word, 16 bits, zero-base numbering system)
The offset of the module in A24 space is set by the upper eight bits (15-8) of
this register. The lower eight bits (7-0) of this register are zero.
13
12
11
10
A21
A20
A19
A18
A24 Offset
*WRITE BITS (A24 Offset Register)
These bits set the offset of the module in A24 space.
**READ BITS (A24 Offset Register)
The module's offset in A24 space.
Data is stored on the module in large, slow dynamic RAM and fast, small
backplane cache. Each of these data stores is a FIFO. The dynamic RAM
FIFO receives the data from the ADC. As soon as the pre-trigger data has
been identified, data is moved from the dynamic RAM FIFO to the
backplane cache FIFO. Data is removed from the module using the cache
FIFO. Data is 16-bit 2's compliment and is packed into the FIFO registers.
Always read register 08h before 0Ah if using D16. The FIFO is incremented
after reading register 0Eh. If D32 is used, reading 08h will increment the
FIFO correctly. The data is interwoven from all channels.
The following is the ordering of the data when D16 is used to remove the
data on a 4-channel module.
- Read 08h channel 1 data (bit 15 is MSB of chan1, bit 0 is LSB of chan 1)
- Read 0Ah channel 2 data
- FIFO is automatically incremented to bring in the next data
9
8
7
A17
A16
0
HP E1563A and E1564A Register-Based Programming 119
6
5
4
3
undefined
0
0
0
0
2
1
0
0
0
0
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