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base + 08
15
14
16
Read
Cache FIFO Low
Word Register
base + 0A
15
14
16
Read
Interrupt Control
Register
base + 0C
15
14
16
Write*
Read**
TRIG DONE PRE OVER CH4
Interrupt Control register bits defined:
bits 0-2
L0-2
bit 3
Enable
120 HP E1563A and E1564A Register-Based Programming
- Read 08h channel 3 data
- Read 0Ah channel 4 data
- FIFO is automatically incremented to bring in the next data
The following is the ordering of the data when D32 is used to remove the
data on a 4-channel module.
- Read 08h channel 1 data, channel 2 data (bit 31 is MSB of chan 1, bit 16 is
LSB of chan 1, bit 15 is MSB of chan 2, bit 0 is LSB of chan 2)
- FIFO is automatically incremented to bring in the next data
- Read 0Ah channel 3 data, channel 4 data (bit 31 is MSB of chan 3, bit 16
is LSB of chan 3, bit 15 is MSB of chan 4, bit 0 is LSB of chan 4)
- FIFO is automatically incremented to bring in the next data
13
12
11
10
13
12
11
10
The interrupt level and the interrupt source are controlled by the interrupt
control register. There are several sources of interrupt. A logical OR is
performed on the enabled sources to determine if an IRQ should be pulled.
This allows a user to set an interrupt if any channel exceeds a predetermined
level or if data is available. Bits 0, 1 and 2 control the interrupt level (1 - 7).
Level 0 (000) is not a valid setting. The enable bit (bit 3) allows an IRQ to
occur when it is set high. All interrupt sources are edge sensitive. If a
masked latched interrupt source is high during the interrupt acknowledge
(iack) cycle, the latch of the source is cleared and will not be set until another
edge from the source occurs.
13
12
11
10
CH3
*WRITE BITS (Interrupt Control Register)
Specifies the interrupt level (1 - 7); "001" = 1, "111" = 7
Enable the interrupt; "1" = interrupt enabled, "0" = interrupt disabled.
9
8
7
6
9
8
7
6
9
8
7
6
CH2
CH1
undefined
5
4
3
2
5
4
3
2
5
4
3
2
Enable
L2
Enable
Interrupt Level
Appendix B
1
0
LSB
1
0
LSB
1
0
L1
L0
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