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Trigger/Interrupt Level Channel 2 register and bit definition:
base + 2A
15
14
16
Write*
MSB-
D6
D7
Read**
MSB-
D6
D7
bit 0
bits 15-8
D7-D0
Trigger/Interrupt
Level Channel 3
Register
base + 2C
15
14
16
Write*
MSB-
D6
D7
Read**
MSB-
D6
D7
Trigger/Interrupt Level Channel 3 register bits defined:
bit 0
bits 15-8
D7-D0
Trigger/Interrupt
Level Channel 4
Register
base + 2E
15
14
16
Write*
MSB-
D6
D7
Read**
MSB-
D6
D7
Trigger/Interrupt Level Channel 4 register bits defined:
bit 0
bits 15-8
D7-D0
126 HP E1563A and E1564A Register-Based Programming
13
12
11
10
D5
D4
D3
D2
D5
D4
D3
D2
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 2 Register)
GL
Greater than or Less than; "0" = >, "1" = <.
data bits.
This register provides 8-bit data corrected for offset and gain in 2's
compliment format.
13
12
11
10
D5
D4
D3
D2
D5
D4
D3
D2
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 3 Register)
GL
Greater than or Less than; "0" = >, "1" = <.
data bits.
This register provides 8-bit data corrected for offset and gain in 2's
compliment format.
13
12
11
10
D5
D4
D3
D2
D5
D4
D3
D2
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 4 Register)
GL
Greater than or Less than; "0" = >, "1" = <.
data bits.
9
8
7
6
D1
D0
0
0
D1
D0
0
0
9
8
7
6
D1
D0
0
0
D1
D0
0
0
9
8
7
6
D1
D0
0
0
D1
D0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
Appendix B
1
0
0
GL
0
GL
1
0
0
GL
0
GL
1
0
0
GL
0
GL
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