Flash Memory - Intel Stratix 10 GX User Manual

Schematic Signal Name
ENET_SGMII_TX_P
ENET_SGMII_TX_N
ENET_SGMII_RX_P
ENET_SGMII_RX_N
ENET_XTAL_25MHZ
ENET_T_INTn
ENET_RSET
MDIO_T
MDC_T
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3

4.11 Flash Memory

The development board has two 1-Gbit CFI compatible synchronous flash device for
non-voltaile storage of the FPGA configuration data, board information, test application
data and user code space.
Two flash devices are implemented to achieve a 32-bit wide data bus at 16 bits each
per device. The target device is a Micron PC28F00AP30BF CFI Flash device. Both MAX
V CPLD and Intel Stratix 10 GX FPGA can access this Flash device.
MAX V CPLD accesses are for AvST configuration of the FPGA at power-on and board
reset events. It uses the PFL Megafunction. Intel Stratix 10 GX FPGA access to the
flash memory's user space is done by Nios II for the BUP application. The flash is
wired for WORD mode operation to support AvSTx32 download directly.
The table below shows the memory map for the on-board flash. This memory provides
non-volatile storage for two FPGA bit-streams as well as various settings for data used
for the Board Update Portal (BUP) image and on-board devices such as PFL II
configuration bits.
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Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
38
Marvell 88E1111 (U23) PHY Pin
Number
82
81
77
75
55
23
30
24
25
29
31
33
34
39
41
42
43
4 Board Components
Description
SGMII transmit
SGMII transmit
SGMII receive
SGMII receive
25 MHz clock
Management bus interrrupt
Device reset
Management bus data input/output
Management bus data clock
Management bus data
Management bus data
Management bus data
Management bus data
Management bus data
Management bus data
Management bus data
Management bus data