Intel Stratix 10 GX User Manual page 39

4 Board Components
Table 20. Flash Memory Map
Block Description
Board Test System
User Software
Factory Software
zipfs
User Hardware 2
User Hardware 1
Factory Hardware
PFL Option Bits
Board Information
Ethernet Option Bits
User Design Reset
Each FPGA bit-stream can be a maximum of 254.25 Mbits (or less than 32 MB) for the
Intel Stratix 10 GX FPGA device. The remaining area is designated as RESERVED flash
area for storage of the BUP image and PFL configuration settings, software binaries
and other data relevant to the FPGA design.
Table 21. Flash Memory Pin Assignments Table
Flash Memory Device Pin
Number (U33/U34)
A1 (U33/U34)
B1 (U33/U34)
C1 (U33/U34)
D1 (U33/U34)
D2 (U33/U34)
A2 (U33/U34)
C2 (U33/U34)
A3 (U33/U34)
B3 (U33/U34)
C3 (U33/U34)
D3 (U33/U34)
C4 (U33/U34)
A5 (U33/U34)
B5 (U33/U34)
C5 (U33/U34)
D7 (U33/U34)
Size
512 KB
14,336 KB
8,192 KB
8,192 KB
44,032 KB
44,032 KB
44,032 KB
64 KB
64 KB
64 KB
64 KB
Schematic Signal Name
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16
® ®
Intel Stratix
0x09F4.0000 - 09FB.FFFF
0x0914.0000 - 09F3.FFFF
0x0894.0000 - 0913.FFFF
0x0814.0000 -0893.FFFF
0x0564.0000 - 0813.FFFF
0x02B4.0000 - 0563.FFFF
0x0004.0000 - 02B3.FFFF
0x0003.0000 - 0003.FFFF
0x0002.0000 - 0002.FFFF
0x0001.0000 - 0001.FFFF
0x0000.0000 - 0000.FFFF
Description
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
10 GX Transceiver Signal Integrity Development Kit User Guide
Address
Intel Stratix 10 Device
Pin Number
BB30
BF31
BG32
BC35
BG29
BG30
BH28
BH31
BF29
BH32
BD29
BC36
BA31
BJ29
BJ30
BA32
continued...
39