Intel Stratix 10 GX User Manual page 18

Signal Name/Function
S10_UNLOCK
ENET_SGMII_TX_P/N
ENET_SGMII_RX_P/N
ENET_RSTn
ENET_INTn
ENET_MDIO
ENET_MDC
SPARE[20:1]
I2C_1V8_SCL
I2C_1V8_SDA
OVERTEMPn
TEMP_ALERTn
CLK_50M_S10
CLK_S10BOT_100M_p/n
CLKIN_SMA_3C_p/n
CLKOUT_SMA_3C_p/n
USB_FPGA_CLK
CLK_S10TOP_ADJ_p/n
CLK_S10TOP_125M_p/n
FACLKM2Cp/n0
FACLKM2Cp/n1
FBCLKM2Cp/n0
FBCLKM2Cp/n1
FACLKBIDIRp/n2
FACLKBIDIRp/n3
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Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
18
I/O Count
1
Ethernet
2
2
1
1
1
1
Other Bus
20
1
1
Temperature
1
1
Global Clocks
1
2
2
2
1
2
2
2
2
2
2
2
2
Transceiver Clocks
4 Board Components
Description
FPGA Unlock Switch
Ethernet SGMII Transmit Data
Ethernet SGMII Receive Data
Reset
Interrupt
Ethernet Management Data I/O
Ethernet Management Data Clock
Spare bus between Intel Stratix 10 and
MAX V
2
Intel Stratix 10 I C bus
2
Intel Stratix 10 I C bus
Intel Stratix 10 over temperature
indicator
Intel Stratix 10 temperature alert
indicator
50 MHz Global Clock Input
100 MHz differential core clock for
bottom banks
Global Clock input from SMA
Dedicated Clock output to SMA
USB FPGA Clock
Adjustable differential core clock for
top banks
125 MHz differential core clock for top
banks
FMC A clock input 0
FMC A clock input 1
FMC B clock input 0
FMC B clock input 1
FMC A bidirectional clock 2
FMC A bidirectional clock 3
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