General-Purpose Clocks - Intel Stratix 10 GX User Manual

In addition to the two oscillators and PLLs, each sides have two dedicated differential
input from a pair of SMA connectors to allow use of lab equipment clock
REFCLK
generators as the transceiver clock source.
The four inputs below connect directly to the transceiver clock inputs:
•
J65/J66 SMA connectors direct connection to
•
J67/J68 SMA connectors direct connection to
•
J69/J70 SMA connectors direct connection to
•
J71/J72 SMA connectors direct connection to
The figure below shows the dedicated transceiver clocks that are implemented on the
Intel Stratix 10 GX FPGA development kit.
Figure 8. Transceiver Dedicated Clocks
OSC
SEL
Trigger
Crystal
Trigger

4.8.2 General-Purpose Clocks

In addtion to transceiver dedicated clocks, five other clock sources are provided to the
FPGA Global
The usage of these clocks is as follows:
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
32
FAGBTCLKM2Cp/n3 (FMCA)
CLK_FMCA_706M_p/n (U4)
FAGBTCLKM2Cp/n2 (FMCA)
Clock
CLK_GXBR4M_625M_p/n (U6)
Buffer
U4
FAGBTCLKM2Cp/n1 (FMCA)
CLK_GXBR4L_644M_p/n (U6)
FAGBTCLKM2Cp/n0 (FMCA)
CLKIN_SMA_4K_p/n (SMA)
CLK_MXP3_706M_p/n (U4)
CLK_GXBR4F_644M_p/n (U6)
CLK_MXP2_706M_p/n (U4)
PLL
CLK_GXBR4E_644M_p/n (U6)
U6
CLK_MXP1_706M_p/n (U4)
CLK_GXBR4D_644M_p/n (U6)
CLK_SMA_706M_p/n (U4)
CLKIN_SMA_4C_p/n (SMA)
inputs for general FPGA design as shown in the figure below.
CLK
REFCLK_GXB1C
REFCLK_GXB1M
REFCLK_GXB4C
REFCLK_GXB4K
Stratix 10 GX
(FMCB) FBGBTCLKM2Cp/n1
4N 1N
(U3) CLK_FMCB_644M_p/n
(FMCB) FBGBTCLKM2Cp/n0
4M 1M
(SMA) CLKIN_SMA_1M_p/n
(U5) CLK_GXBR1L_625M_p/n
4L 1L
(U3) CLK_SFP_644M_p/n
4K 1K
(U5) CLK_GXBL1K_614M_p/n
(U5) CLK_GXBL1F_625M_p/n
4F 1F
(U5) CLK_GXBL1E_614MT_p/n
4E 1E
(U5) CLK_GXBL1E_614MT_p/n
(U3) CLK_QSFP0_644MT_p/n
4D 1D
(U3) CLK_QSFP0_644MB_p/n
(U3) CLK_CFP4_644M_p/n
4C 1C
(SMA) CLKIN_SMA_1C_p/n
4 Board Components
block
block
block
block
Clock
OSC
Buffer
U3
SEL
Trigger
PLL
U5
Crystal
Trigger