Intel Stratix 10 GX User Manual page 15

4 Board Components
Signal Name/Function
FPGA_CONFIG_D[31:0]
FPGA_AS_DATA[3:0]
FPGA_AVST_READY
FPGA_AVST_VALID
FPGA_AVST_CLK
FPGA_PR_DONE
FPGA_PR_REQUEST
FPGA_PR_ERROR
NPERSTL, NPERSTR
FPGA_SDM10
FPGA_CvP_DONE
FPGA_SEU_ERR
VCC_SDA/VCC_SCL
VCC_ALERTn
SFP0_TX_DS
SFP0_RS[1:0]
SFP0_MOD_ABS
SFP0_RX_LOS
SFP0_TX_FLT
SFP0_SCL
SFP0_SDA
SFP1_TX_DIS
SFP1_RS[1:0]
SFP1_MOD_ABS
SFP1_RX_LOS
SFP1_TX_FLT
SFP1_SCL
SFP1_SDA
CFP4_MOD_LOPWR
CFP4_MOD_RSTn
CFP4_GLB_ALRMN
I/O Count
32
4
1
1
1
1
1
1
4
1
1
1
2
1
Transceivers
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
Description
Configuration input pin that enables all
IOs
EPCQL data bus
SDM ready for AvST configuration
scheme
Data valid for AvST configuration
scheme
Configuration clock for AvST
configuration scheme
Partial reconfiguration done pin
Partial reconfiguration request pin
Partial reconfiguration error pin
Reset pin for PCIe HIP
SDM IO 10
CvP configuration done pin
SEU error indicate pin
SmartVID PMBus
SmartVID PMBus
SFP+ 0 TX disable control Pin
SFP+ 0 Rate Select Control Pin
SFP+ 0 Module Absent Status Pin
SFP+ 0
SFP+ 0 Transmitter Fault Status Pin
SFP+ 0 Management Data Clock
SFP+ 0 Management Data I/O Bi-
Directional Data
SFP+ 1 TX disable control pin
SFP+ 1 Rate Select Control Pin
SFP+ 1 Module Absent Status Pin
SFP+ 1
SFP+ 1 Transmitter Fault Status Pin
SFP+ 1 Management Data Clock
SFP+ 1 Management Data I/O Bi-
Directional Data
CFP4 Module Low Power Mode
CFP4 Module Reset
CFP4 Program Alarm bits
continued...
15