Communication Ports - Intel Stratix 10 GX User Manual

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Table of Contents

4 Board Components

Table 17.

FMC Interface

Schematic Signal Name

FAC2Mp/n[23:0]

FAM2Cp/n[23:0]

FBC2Mp/n[15:0]

FBM2Cp/n[15:0]

Table 18.

External Loopback Interface

Schematic Signal Name

GXBL_1F_TXp/n[5:0]

GXBL_1F_RXp/n[5:0]

4.10 Communication Ports

The Intel Stratix 10 GX transceiver signal integrity development board supports a

10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the

Intel Triple-Speed Ethernet Megacore MAC function. The device is an auto-negotiating

Ethernet PHY with an SGMII interface to the FPGA.

The Intel Stratix 10 GX FPGA device can communicate with the LVDS interfaces at up

to 1.25 Gbps. The MAC function is provided in the FPGA for typical networking

applications. The Marvell 88E1111 PHY uses 2.5 V and 1.2 V power rails and requires

a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45

connector with internal magnetics that are used for driving copper lines with Ethernet

traffic.

Table 19.

Ethernet PHY Pin Assignments

Schematic Signal Name

ENET_LED_LINK1000

ENET_LED_LINK100

ENET_LED_LINK10

ENET_LED_TX

ENET_LED_RX

Intel Stratix 10 FPGA Pin Number