Intel Stratix 10 GX User Manual page 70

Status
Displays the following status information during a loopback test:
• PLL Lock: Shows the PLL locked or unlocked state.
• Pattern Sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
• Details: Shows the PLL lock and pattern status:
Port
Allows you to specify which interface to test. The following port tests are available:
• MXP0 x4
• MXP1 x4
• MXP2 x4
PMA Setting
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
• Serial Loopback: Routes signals between the transmitter and the receiver.
• VOD: Specifies the voltage output differential of the transmitter buffer.
• Pre-emphasis tap:
— 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
— 2nd pre (L-Tile): Specifies the amount of pre-emphasis on the second pre-tap
of the transmitter buffer.
— 1st post: Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
— 2nd post (L-Tile): Specifies the amount of pre-emphasis on the second post-
tap of the transmitter buffer.
• Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage
mode.
• DC gain: Specifies the DC gain setting for the receiver equalizer in four stage
mode.
• VGA: Specifies the VGA gain value.
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Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
70
6 Board Test System