Intel Stratix 10 GX User Manual page 33

4 Board Components
• 50 MHz oscillator through an SL18860 buffer for Nios II applications.
USB_FPGA_CLK
• 25 MHz crystal supplied to an ICS557-03 Spread Spectrum differential clock
buffer. The available frequencies and down spread percentages available from the
spread spectrum buffer as shown in the table below.
• External differential clock source from SMA connectors. Dedicated differential
output clock to SMA connectors.
• Three clock outputs are provided from two Si5341 PLLs:
—
CLK_S10_BOT_100M: 100 MHz LVDS standard
—
CLK_S10_TOP_125M: 125 MHz LVDS standard
—
FPGA_OSC_CLK_1: 125 MHz 1.8V CMOS standard
• Another clock source is clock from FMC daughter cards.
Figure 9. FPGA Clocks
CLK_S10TOP_125M_p/n
FPGA_OSC_CLK_1
CLKOUT_SMA_3C_p/n
CLKIN_SMA_3C_p/n
Table 12. Spread Spectrum Clock Settings and Frequencies
Spread Spectrum Buffer (Inputs)
SS1/S1
0
drives from on-board Intel FPGA Download Cable circuit.
FACLKBIDIRp/n2 (FMCA)
FACLKBIDIRp/n3 (FMCA)
FACLKM2Cp/n1 (FMCA)
FALAp/n17 (FMCA)
(U6)
FAHAp/n0 (FMCA)
FAHAp/n17 (FMCA)
(U6)
(SMA)
(SMA)
CLK_50M_S10 (U1)
SS0/S0
0
®
Intel Stratix
Stratix 10 GX
(U2)
3L 2N
(FMCB)
(FMCB)
3K 1M
(FMCB)
(FMCA)
3J 2L
(FMCA) FALAp/n0
3I
(U9)
SDM 2F
3C 2C
3B 2B
3A 2A
(U5)
Output Clock Select
(MHz)
25 (Default)
®
10 GX Transceiver Signal Integrity Development Kit User Guide
CLK_S10TOP_ADJ_p/n
FBCLKM2Cp/n1
FBCLKM2Cp/n0
FABLp/n0
FACLKM2Cp/n0
USB_FPGA_CLK
CLK_S10BOT_100M_p/n
Spread (%)
Center+/-0.25
continued...
33