Intel Stratix 10 GX User Manual page 22

Signal Name
SI5341_2_LOLn
EN_MASTER[1:0]
TEMP_ALERTn
OVERTEMPn
OVERTEMP
FAN_RPM
USB_CFG[14:0]
USB_MAX5_CLK
MAX_OSC_CLK_1
MAX5_JTAG_TCK
MAX5_JTAG_TMS
MAX5_JTAG_TDI
MAX5_JTAG_TDO
FACTORY_LOAD
MAX5_SWITCH [2:0]
PGM_SEL
PGM_CONFIG
MAX_RESETn
CPU_RESETn
PGM_LED[2:0]
MAXV_ERROR
MAXV_LOAD
MAXV_CONF_DONE
MAX5_BE_n[3:0]
MAX5_OEn
MAX5_CSn
MAX5_WEn
MAX5_CLK
SPARE[20:1]
CLK_50M_MAX5
FPGA_ASDATA[3:0]
CLK_CONFIG
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Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
22
Description
SI5341 2 loss of clock indicators
ENABLE specific I2C buffer
FPGA temperature alert input
FPGA over temperature input
Over temperature fan control
Fan speed control
Bus between USB Intel MAX 10 and MAX V
Clock from USB PHY chip
25MHz / 100 MHz / 125 MHz clock input
MAX V Test Clock
MAX V Test Mode Select
MAX V Test Data Input
MAX V Test Data Output
Factory image for configuration
System MAX V user DIP switch
Flash Memory program select pushbutton
Flash Memory program configuration pushbutton
System MAX V reset pushbutton
CPU reset pushbutton
Flash image program select indicators
Intel Stratix 10 configuration error indicator LED
Intel Stratix 10 configuration active indicator LED
Intel Stratix 10 configuration done indicator LED
Intel Stratix 10 and MAX V data path, byte enable
Intel Stratix 10 and MAX V data path, output enable
Intel Stratix 10 and MAX V data path, chip select
Intel Stratix 10 and MAX V data path, write enable
Intel Stratix 10 and MAX V data path, clock
Spare bus between MAX V and Intel Stratix 10
50 MHz clock input
Intel Stratix 10 AS configuration data
100 MHz clock input
4 Board Components