Intel Stratix 10 GX User Manual page 13

4 Board Components
Board Reference
Y2
U3, U4, U5
U6
J61, J63
J62, J64
J65-J66
J67-J68
J69-J70
J71-J72
X4
J33, J44, J50
J31-J32
J34-J43
J45-J49
J51-J57
J29-J30
J27-J28
J24
J58-J59
U21-U22
Type
Transceiver Dedicated Reference Clock/
Programmable PLL
External core clock input
External core clock output
External transceiver clock input
100-MHz Oscillator
Transceiver Interfaces
MXP connector
2.4 mm RF connector
SFP+ optical transceiver interface
QSFP28 optical transceiver interface
CFP4 optical transceiver interface
FMC+ connector
Memory Devices
Flash Memory
Communication Ports
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
Description
Feeds s on right side of the
REFCLK
Intel Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J8/J9.
The external input is available at board
reference J6 and J7. The default
frequency is 706.25 MHz.
Feeds s on left side of the Intel
REFCLK
Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J10/J11.
The default frequencies are 625 MHz,
614.4 MHz, 100 MHz.
Feeds s on right side of the
REFCLK
Intel Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J12/J13.
The default frequencies are 625 MHz,
644.53125 MHz, 125 MHz.
SMA external input at
CLKIN_3C0
SMA external output at
PLL_3C_CLKOUT0
SMA external input bank at 1C
SMA external input bank at 1M
SMA external input bank at 4C
SMA external input bank at 4K
This 100-MHz oscillator provides clock
to the MAX V CPLD
17 Gbps/28 Gbps, 4 channels MXP
connectors
17 Gbps/ 28 Gbps, 6 channels 2.4 mm
RF connectors
17 Gbps/28 Gbps, 2 channels
connected to SFP+ modules
17 Gbps/28 Gbps, 8 channels
connected to QSFP28 modules
17 Gbps/ 28 Gbps, 4 channels
connected to CFP4 module
17 Gbps/28 Gbps, 34 channels
connected to FMC+ connectors
Two 1-Gbit Micron PC28F00AP30BF CFI
Flash device
continued...
13