Stratix 10 Gx Fpga - Intel Stratix 10 GX User Manual

Board Reference
J19
CN1
U15
U63-U64
U66-U67
U68
U69
U70
U71
U74
U78
U79
U82

4.2 Stratix 10 GX FPGA

The development board features the Intel Stratix 10 GX FPGA (1SG280UF50).
Intel Stratix 10 GX FPGA I/O Usage Summary
Table 4. Stratix 10 GX FPGA Pin Table
Signal Name/Function
S10_JTAG_TCK/TDO/TDI/TMS
FPGA_MSEL[2:0]
FPGA_CONF_DONE
FPGA_nSTATUS
FPGA_INIT_DONE
FPGAMSEL0
FPGA_nCONFIG
FPGA_OSC_CLK_1
FPGA_AS_CLK
CPU_RESETn
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
14
Type
Gigabit Ethernet Port
USB Type-B connector
Power Supply
LTM2987
LTM4677
3x LTM4650
LTM4620
LTM4620
LTM4620
LTM4620
EN63A0
EN63A0
EN6337
LTM4630A
I/O Count
Configuration
4
2
1
1
1
1
1
1
1
1
4 Board Components
Description
RJ-45 connector which provides a
10/100/1000 Ethernet connection
through a Marvell 88E1111 PHY
Connects a type-B USB cable
Linear Technology power monitor
device
Power regulators for rail
VCC
Power regulators for
VCCERAM
Power regulators for rail
VCCH
Power regulators for rail
VCCRL
Power regulators for rail
VCCRR
Power regulators for
FMCA_VADJ
Power regulators for
FMCB_VADJ
Power regulators for rail
2.5V
Power regulators for rail
3.3V
Description
JTAG Configuration Pins
Configuration input pins to set
configuration scheme
Configuration done pin
Configuration status pin
Configuration pin to signify user mode
Configuration input pins to set
configuration scheme and Chip select
pin to EPCQL device
Configuration input pin to reset FPGA
125 MHz Clock
Configuration Clock for AS
configuration schemes
Global reset signal
continued...
rail
rail
rail