Intel Stratix 10 GX User Manual page 79

6 Board Test System
• PLL lock: Shows the PLL locked or unlocked state
• Pattern Sync: Shows the pattern synced or not state. The pattern is considered
synced when the start of the data sequence is detected.
• Details: Shows the PLL lock and pattern sync status.
Port
Use the following controls to select an interface to apply PMA settings, data type and
error control:
• CFP4 x4
PMA Setting
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
1. Serial Loopback: Routes signals between the transmitter and the receiver.
2. VOD: Specifies the voltage output differential of the transmitter buffer.
3. Pre-emphasis tap:
• 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
• 2nd pre: Specifies the amount of pre-emphasis on the second pre-tap of the
transmitter buffer.
• 1st post: Specifies the amount of pre-emphasis on the first post tap of the
trasnmitter buffer.
• 2nd post: Specifies the amount of pre-emphasis on the second post tap of the
transmitter buffer.
4. Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage
mode.
5. DC Gain: Specifies the DC Gain setting for the receiver equalizer in four stage
mode.
6. VGA: Specifies the VGA gain value.
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
79