Fpga Programming Over External Usb-Blaster - Intel Stratix 10 GX User Manual

After a POWER-ON or RESET (reconfiguration) event, the MAX V device shall configure
the Intel Stratix 10 GX FPGA in the AvSTx32 mode with either the
an
USER DEFINED POF
The
MSEL[2:0]
manufacturing default condition is
For different configuration modes, MSEL [2:0] signals must be set acccording to the
table below:
Table 6. Support Configuration Modes for Stratix 10 Transceiver Signal Integrity
Development Kit
Configuration Scheme
Avalon-ST (x32)
Avalon-ST (x16)
AS (Normal mode)
JTAG only
Not supported

4.4.3 FPGA Programming over External USB-Blaster

The JTAG chain allows programming of both the Intel Stratix 10 GX FPGA and MAX V
CPLD devices using an external USB-Blaster dongle or the on-board USB-II Blaster via
the USB Interface Connector.
During board bring-up, and as a back-up in case the on-board USB-Blaster II has a
problem, the external USB-Blaster dongle can be used to program both the Intel
Stratix 10 and MAX V CPLD via the external blaster 2x5 pin 0.1" programming header
(J14)
Another 2x5 pin 0.1" vertical non-shrouded header (J15) is provided on the board for
programming the Intel MAX 10_Blaster FPGA for configuring the on-board USB Blaster
circuitry. Once the on-board Blaster is configured and operational, the on-board
blaster can be used for subsequent programming of the Intel Stratix 10 GX FPGA and
MAX V CPLD.
The on-board blaster JTAG chain connects four JTAG nodes in the following order, with
the option to bypass the Intel Stratix 10, MAX V, FMC A or FMC B by a dip switch SW3
setting as follows:
• Switch closed/ON: Corresponding JTAG node is bypassed.
• Switch open/OFF: Corresponding JTAG node is enabled in the JTAG chain.
Pin 2 of the J14 Header is used to disable the embedded USB Blaster by connecting it
to the embedded Blaster's low active disable pin with a pull-up resistor. Since Pin 2
from the mating Blaster dongle is
header, the embedded Blaster is disabled to avoid contention with the external USB
Blaster dongle.
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
26
depnding on the
pins indicate which configuration scheme is chosen. The
[000]
000
101
011
111
Other Settings
, when the dongle is connected into the JTAG
GND
setting.
FACTORY_LOAD
for AvSTx32 scheme.
MSEL [2:0]
4 Board Components
or
FACTORY POF