Intel Stratix 10 GX User Manual page 62

• PLL Lock: Shows the PLL locked or unlocked state.
• Pattern Sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
• Details: Shows the PLL lock and pattern status:
Port
Allows you to specify which interface to test. The following port tests are available:
XCVR and CMOS
PMA Setting
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
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Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
62
6 Board Test System