Intel Stratix 10 GX User Manual page 36

Table 15. MXP Interface
Schematic Signal Name
GXBL_4D_TXp/n[1:0][4:3]
GXBL_4D_RXp/n[1:0][4:3]
GXBL_4E_TXp/n[1:0][4:3]
GXBL_4E_RXp/n[1:0][4:3]
GXBL_4F_TXp/n[1:0][4:3]
GXBL_4F_RXp/n[1:0][4:3]
Figure 11. MXP connector pin function mapping
Table 16. Optical Modules Interface
Schematic Signal Name
GXBL_1C_TXp/n[1:0][4:3]
GXBL_1C_RXp/n[1:0][4:3]
GXBL_1D_TXp/n[1:0][4:3]
GXBL_1D_RXp/n[1:0][4:3]
GXBL_1E_TXp/n[1:0][4:3]
GXBL_1E_RXp/n[1:0][4:3]
GXBL_1K_TXp/n 0/3
GXBL_1K_RXp/n 0/3
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
36
Stratix 10 FPGA Pin Number
Positive pin location increases from
index 0: BD1, BA3, AW3, AY1
Positive pin location increases from
index 0: BA7, BB5, AY5, AU7
Positive pin location increases from
index 0: AV1, AR3, AP1, AN3
Positive pin location increases from
index 0: AR7, AT5, AN7, AM5
Positive pin location increases from
index 0: AK1, AL3, AJ3, AF1
Positive pin location increases from
index 0: AL7, AH5, AF5, AG7
RXN0 RXP0 RXN1 RXP1
8 7 6 5
9 10 11 12
TXN0 TXP0 TXN1 TXP1
Intel Stratix 10 FPGA Pin Number
Positive pin location increases from
index 0: BJ46, BF45, BE47, BF49
Positive pin location increases from
index 0: BH41, BJ43, BE43, BC43
Positive pin location increases from
index 0: BD49, BA47, AW47, AY49
Positive pin location increases from
index 0: BA43, BB45, AY45, AU43
Positive pin location increases from
index 0: AV49, AR47, AP49, AN47
Positive pin location increases from
index 0: AR43, AT45, AN43, AM45
Positive pin location increases from
index 0: AE47, AA47
Positive pin location increases from
index 0: AC43, AB45
Description
MXP 1 GXB Transmitter
MXP 1 GXB Receiver
MXP 2 GXB Transmitter
MXP 2 GXB Receiver
MXP 3 GXB Transmitter
MXP 3 GXB Receiver
RXN3 RXP3 RXN4 RXP4
4 3 2 1
13 14 15 16
TXN3 TXP3 TXN4 TXP4
Description
CFP4 GXB Transmitter
CFP4 GXB Receiver
QSFP28 0 GXB Transmitter
QSFP28 0 GXB Receiver
QSFP28 1 GXB Transmitter
QSFP28 1 GXB Receiver
SFP+ 0/1 GXB Transmitter
SFP+ 0/1 GXB Receiver
4 Board Components