Intel Stratix 10 GX User Manual page 25

4 Board Components
Figure 6. MAX V + Flash AvSTx32 Configuration Block Diagram
X4 100 MHz
U1 50 MHz
U9 48 MHz
D23
D24
D25
D20
D21
D22
S12
S11
Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its
Flash interface signals to avoid contention with the FPGA. The
is provided to select between two
The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx32
configuration in the MAX V CPLD. The PFL II Megafunction reads data from the flash
and converts it to AvST format. This data is written into the Intel Stratix 10 GX FPGA
device through dedicated AvST CLK and FPGA Config Data [31:0] pins at
corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.
Implementation will be done using an Intel MAX V 5M2210ZF256FBGA CPLD acting as
the AvST download controller and two 1G Flash devices. The Flash will be Numonyx
1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX V
CPLD shares the CFI Flash interface with the Intel Stratix 10 GX FPGA. No arbitration
is needed between MAX V CPLD and Intel Stratix 10 GX FPGA to access the Flash as
the CPLD only has access prior to FPGA initialization.
MAX_OSC_CLK_1
MAX V System Controller
5M2210ZF256
CLK_CONFIG
nCONFIG
CLK_50M_MAX5
nSTATUS
CONF_DONE
USB_MAX5_CLK
INIT_DONE
Error
ERROR
AvST_READY
LOAD
LOAD AvST_CLK
FPGA_DATA[31:0]
CONF_DONE
CONF_DONE
AvST_VALID
PGM0 PGM_LED0
FA[26:1]
PGM1 PGM_LED1
FOEn
PGM_LED2
PGM2
FWEn
Factory Load
FWPn
MAX V Switch FADVn
SW6
MAX V Switch WAIT
MAX V Switch FRSTn
FLASH_D[31:0]
MAX_RESETn
PGM_CONFIG
PGM_SEL
S10
CPU_RESETn
S13
®
Intel Stratix
FPGA_OSC_CLK_1
U6
125 MHz
FCLK
FCEn
PC28F00AP30BF
Flash (1G)
FA[26:1]
FD[15:0]
CLK
CEn
OEn
WEn
WPn
ADVn
WAIT
RESETn
PC28F00AP30BF
Flash (1G)
FA[26:1]
FD[15:0]
CLK
CEn
OEn
WEn
WPn
ADVn
WAIT
RESETn
files ( and
POF FACTORY
®
10 GX Transceiver Signal Integrity Development Kit User Guide
Intel Stratix 10 GX
OSC_CLK_1
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
AvST_READY
AvST_CLK
D[31:0]
AvST_VALID
FA[26:1]
FCLK
FCEn
FOEn
FWEn
MSEL0 SW11
FWPn
MSEL1
SW10
FADVn
MSEL2
WAIT
CPU_RESET
RESETn
FLASH_D[31:0]
dipswitch (S10)
PGMSEL
) stored on the Flash.
USER
25