Mitsubishi Q01CPU User Manual page 662

12
TROUBLESHOOTING
Number Name Meaning
Maximum
number of blocks
used for the
multiple CPU
high-speed
SD796
transmission
dedicated
instruction
setting (for CPU
No.1)
Maximum
number of blocks
used for the
multiple CPU
high-speed
Maximum
SD797
transmission
number of blocks
dedicated
range for
instruction
dedicated
setting (for CPU
instructions
No.2)
Range: 1 to 7
Maximum
(Default: 2 Or
number of blocks
when setting
used for the
other than 1 to 7,
multiple CPU
the register
high-speed
SD798
operates as 7).
transmission
dedicated
instruction
setting (for CPU
No.3)
Maximum
number of blocks
used for the
multiple CPU
high-speed
SD799
transmission
dedicated
instruction
setting (for CPU
No.4)
*14: The Universal model QCPU except the Q02UCPU.
*15: The range is from 1 to 9 for the Q03UDCPU, Q04UDHCPU, and Q06UDHCP whose first 5 digits of serial number is "10012" or earlier.
(Default: 2 Or when setting other than 1 to 9, the register operates as 9).
12
- 338 12.8 Special Register List
Table12.51 Special register
Explanation
• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.1).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.1, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM796 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.
• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.2).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.2, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM797 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.
• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.3).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.3, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM798 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.
• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.4).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.4, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM799 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.
Corres-
Set by ponding Corresponding
ACPU
(When Set)
D9
U (At 1 scan
New
after RUN)
U (At 1 scan
New
after RUN)
QnU
U (At 1 scan
New
after RUN)
U (At 1 scan
New
after RUN)
CPU
*14*15