Mitsubishi QCPU (Q Mode) User Manual

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High Performance Model QCPU(Q Mode)

User's Manual

(Function Explanation,

Program Fundamentals)

Mitsubishi Programmable

Logic Controller

Table of Contents

Summary of Contents for Mitsubishi QCPU (Q Mode)

Page 1 High Performance Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals) Mitsubishi Programmable Logic Controller...
Page 2: Safety Instructions
• SAFETY INSTRUCTIONS • (Always read these instructions before using this equipment.) When using Mitsubishi equipment, thoroughly read this manual and the associated manuals introduced in this manual. Also pay careful attention to safety and handle the module properly. These SAFETY PRECAUTIONS classify the safety precautions into two categories: "DANGER" and "CAUTION".
Page 3 [Design Precautions] DANGER • When overcurrent which exceeds the rating or caused by short-circuited load flows in the output module for a long time, it may cause smoke or fire. To prevent this, configure an external safety circuit, such as fuse. •...
Page 4 [Installation Precautions] CAUTION • Use the PLC in an environment that meets the general specifications contained in High Performance model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection). Using this PLC in an environment outside the range of the general specifications could result in electric shock, fire, erroneous operation, and damage to or deterioration of the product.
Page 5 [Wiring Precautions] CAUTION • Be sure to ground the FG terminals and LG terminals to the protective ground conductor. Not doing so could result in electric shock or erroneous operation. • When wiring in the PLC, be sure that it is done correctly by checking the product's rated voltage and the terminal layout.
Page 6 [Startup and Maintenance precautions] CAUTION • The online operations conducted for the CPU module being operated, connecting the peripheral device (especially, when changing data or operation status), shall be conducted after the manual has been carefully read and a sufficient check of safety has been conducted. Operation mistakes could cause damage or problems with of the module.
Page 7: Revisions
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 8: Table Of Contents
INTRODUCTION Thank you for choosing the Mitsubishi MELSEC-Q Series of General Purpose Programmable Controllers. Please read this manual carefully so that equipment is used to its optimum. CONTENTS SAFETY INSTRUCTIONS ............................A- 1 REVISIONS ..................................A- 6 CONTENTS..................................A- 7 Manuals..................................A-17 How to Use This Manual.............................. A-18 Generic Terms and Abbreviations..........................
Page 9 4.6 Data Clear Processing ............................4-38 4.7 I/O Processing and Response Lag........................4-39 4.7.1 Refresh mode............................ 4-39 4.7.2 Direct mode ............................4-42 4.8 Numeric Values which Can Be Used in Sequence Programs ................4-44 4.8.1 BIN (Binary code) ..........................4-46 4.8.2 HEX (Hexadecimal)........................... 4-47 4.8.3 BCD (Binary Coded Decimal) ......................
Page 10 7.4 Setting the Output (Y) Status when Changing from/to STOP Status to/from RUN Status ......7- 7 7.5 Clock Function .................................7- 9 7.6 Remote Operation ..............................7-12 7.6.1 Remote RUN/STOP.......................... 7-12 7.6.2 Remote PAUSE..........................7-15 7.6.3 Remote RESET..........................7-17 7.6.4 Remote latch clear ..........................7-19 7.6.5 Relationship of the remote operation and High Performance model QCPU RUN/STOP switch...
Page 11 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE 8- 1 to 8- 9 8.1 Communication Between High Performance model QCPU and Q-series Intelligent Function Modules..8- 1 8.1.1 Initial setting and automatic refresh setting using GX Configurator ..........8- 2 8.1.2 Communication using device initial value..................8- 3 8.1.3 Communication using FROM/TO instruction ...................
Page 12 10.6 Index Registers (Z)..............................10-39 10.6.1 Switching between scan execution type programs and low speed execution type programs ... 10-40 10.6.2 Switching between scan/low speed execution type programs and interrupt/ fixed scan execution type programs .................... 10-41 10.7 File Registers (R)..............................10-43 10.7.1 File register capacity ........................
Page 13 13 OUTLINE OF MULTIPLE PLC SYSTEMS 13- 1 to 13- 6 13.1 Features................................13- 1 13.2 Outline of Multiple PLC Systems ........................13- 3 13.3 Differences with Single CPU Systems ......................13- 5 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEMS 14- 1 to 14- 20 14.1 System Configuration............................14- 1 14.2 Precautions For Multiple PLC System Configuration..................14- 4 14.2.1 Function versions of High Performance model QCPU , motion CPUs and...
Page 14 18 PROCESSING TIME FOR MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL QCPUs 18- 1 to 18- 3 18.1 Concept behind CPU Scanning Time......................18- 1 18.2 Factor to Prolong the Scan Time........................18- 2 19 STARTING UP THE MULTIPLE PLC SYSTEM 19- 1 to 19- 9 19.1 Flow-chart for Starting Up the Multiple PLC System ..................19- 1 19.2 Setting Up the Multiple PLC System Parameters (Multiple PLC Settings, Control PLC Settings)....19- 3 19.2.1 System configuration........................
Page 15: Contents
(Related manual)..............High Performance Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection) CONTENTS 1. OVERVIEW 1.1 Features 2. SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM 2.1 System Configuration 2.2 Precaution on System Configuration 2.3 Comfirming Serial Number and Function Version 3.
Page 16 7. MEMORY CARD AND BATTERY 7.1 Memory Card Specifications 7.2 Battery Specifications (For CPU Module and SRAM Card) 7.3 Handling the Memory Card 7.4 The Names of The Parts of The Memory Card 7.5 Memory Card Loading/Unloading Procedures 7.6 Installation of Battery (for CPU Module and Memory Card) 8.
Page 17 11. TROUBLESHOOTING 11.1 Troubleshooting Basics 11.2 Troubleshooting 11.2.1 Troubleshooting flowchart 11.2.2 Flowchart when "MODE" LED is not turned on 11.2.3 When "MODE" LED is flickering 11.2.4 Flowchart when "POWER" LED is turned off 11.2.5 Flowchart when the "RUN" LED is turned off 11.2.6 When the "RUN"...
Page 18: Manuals
Manuals The following manuals are also related to this product. In necessary, order them by quoting the details in the tables below. Related Manuals Manual Number Manual Name (Model Code) High Performance Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection) SH-080037 (13JL97)
Page 19: How To Use This Manual
How to Use This Manual This manual is prepared for users to understand memory map, functions, programs and devices of the CPU module when you use MELSEC-Q Series PLCs. The manual is classified roughly into three sections as shown below. (1) Chapters 1 and 2 Describe the outline of the CPU module and the system configuration.
Page 20: Generic Terms And Abbreviations
General name for Q02HCPU, Q06HCPU Q12HCPU, and Q25HCPU QnHCPU Abbreviation for Mitsubishi MELSEC-Q Series Programmable Logic Controller. Q Series Abbreviation for small types of Mitsubishi MELSEC-A Series Programmable Logic AnS Series Controller. General product name for SWnD5C-GPPW-E, SWnD5C-GPPW-A-E, SWnD5C- GX Developer GPPW-V-E, SWnD5C-GPPW-VA-E.
Page 21: Overview
1 OVERVIEW MELSEC-Q 1. OVERVIEW This User's Manual describes the hardware specifications and handling methods of the High Performance model QCPU. The Manual also describes those items related to the specifications of the power supply module, main base unit, extension base unit, extension cable, memory card and battery.
Page 22: Features
1 OVERVIEW MELSEC-Q 1.1 Features High Performance model QCPU has the following new features: (1) Controllable multiple I/O points All High Performance model QCPUs support 4096 points (X/Y0 to FFF) as the number of actual I/O points capable of getting access to the I/O module installed on the base unit.
Page 23 1 OVERVIEW MELSEC-Q (6) Saved space by a reduction in size The installation space for Q series has been reduced by approx. 60 % of the space for AnS series. Comparison of installation space 1SX10 1SY50 1SX41 1SY41 1SX81 1SY81 1SX42 1SY42 98mm...
Page 24 1 OVERVIEW MELSEC-Q (9) Data can be written automatically to standard ROM You need not use GX Developer to write parameters/programs on a memory card to the standard ROM of the High Performance model QCPU. When the standard ROM is used to perform ROM operation, you can load a memory card into the High Performance model QCPU and write parameters/programs on the memory card to the standard ROM.
Page 25: Programs
1 OVERVIEW MELSEC-Q 1.2 Programs (1) Program management by memory card Programs created with GX Developer can be stored in the QCPU's program memory, standard ROM or memory card. QCPU Program memory Parameter Program Memory card Standard ROM Parameter Parameter Program Program File register...
Page 26 1 OVERVIEW MELSEC-Q Programs stored in the standard ROM/memory card are executed after they are booted to (read to) the QCPU program memory. (Programs to be booted to the QCPU are designated on the “(PLC) Parameter" dialog box, and the parameter drive is designated by a DIP switch setting at the QCPU.) QCPU Program memory...
Page 27 1 OVERVIEW MELSEC-Q Example of programs split by process: QCPU Program memory / Standard ROM / Memory card Ship in Program A Split Programs A to D Manufacturing Program B are executed in process sequence. Assembly Program C Ship out Program D Example of programs split by function: QCPU...
Page 28: Convenient Programming Devices And Instructions
1 OVERVIEW MELSEC-Q 1.3 Convenient Programming Devices and Instructions The QCPU features devices and instructions which facilitate program creation. Some of them are described below. (1) Flexible device designation (a) Word device bits can be designated to serve as contacts or coils. [In the case of QCPU] [In the case of AnS] Bit designation of...
Page 29 1 OVERVIEW MELSEC-Q The buffer memory of intelligent function module (e.g. Q64AD, Q62DA) can be used in the same way as devices when programming. [In the case of QCPU] [In the case of AnS] U4\G12 FROMP Readout of Q64AD buffer memory's address 12 data :U4\G12 Buffer memory address...
Page 30 1 OVERVIEW MELSEC-Q (2) Edge relays simplify pulse conversion processing The use of a relay (V) that comes ON at the leading edge of the input condition simplifies pulse processing when a contact index qualification has been made. [Circuit example] M1000 Reset index register (Z1) K1000...
Page 31 1 OVERVIEW MELSEC-Q Data processing instructions such as table processing instructions, etc., enable high speed processing of large amounts of data. FINSP FIF0 table FIF0 table Insertion position Insertion Insertion source designation Instruction for data insertion at table Easy shared use of sub-routine programs A common pointer can be used to call the same sub-routine program from all sequence programs being executed.
Page 32: System Configuration For Single Cpu System
2.1 System Configuration The outline of the equipment configuration, configuration with peripheral devices, and system configuration in the High Performance model QCPU system is described below. (1) Equipment configuration MITSUBISHI MITSUBISHI LITHIUM BATTERY Memory card High Performance model QCPU Battery...
Page 33 2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM MELSEC-Q (2) Configuration of peripheral devices MITSUBISHI USB cable 1 Memory card High Performance model QCPU (To be procured yourself) (Q2MEM-1MBS,Q2MEM-2MBS, (Q02CPU,Q02HCPU,Q06HCPU, Only Q02HCPU, Q06HCPU Q2MEM-2MBF,Q2MEM-4MBF, Q12HCPU,Q25HCPU) Q12HCPU and Q25HCPU can be used.
Page 34 2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM MELSEC-Q (3) Outline of system configuration Main base unit(Q312B) Power supply module Slot No. 0 1 2 3 4 5 6 7 8 9 10 11 Extension cable Extension base unit(Q612B) Power supply module The figure shows the configuration 1st extension stage...
Page 35: Precaution On System Configuration
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM MELSEC-Q 2.2 Precaution on System Configuration This section describes hardware and software packages compatible with QCPU. (1) Hardware (a) The number of modules to be installed and functions are limited depending on the type of the modules. Limit of number of modules Applicable Module Type...
Page 36 2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM MELSEC-Q (d) The modules shown below cannot be used. Module Name Type MELSECNET/IO network A1SJ71LP21, A1SJ71BR11, A1SJ71QLP21, module A1SJ71QLP21S, A1SJ71QLP21GE, A1SJ71QBR11 MELSECNET (II), /B data link A1SJ71AP21, A1SJ71AR21, A1SJ71AT21B module A1SJ71QE71-B2-S3(-B5-S3), Ethernet interface module A1SJ71E71-B2-S3(-B5-S3) Serial communication module, A1SJ71QC24(N), A1SJ71UC24-R2(-R4/-PRF)
Page 37 2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM MELSEC-Q 2.3 Confirming the Serial Number and Function Version The CPU module serial No. can be confirmed on the rated plate and GX Developer's system monitor. (1) Confirming the serial No. on the rated plate Serial No.
Page 38: Performance Specification
3 PERFORMANCE SPECIFICATION MELSEC-Q 3. Performance Specification The table below shows the performance specifications of the CPU module. Performance Specifications Model Item Remark Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Control method Repetitive operation of stored program Direct I/O is possible by I/O control mode Refresh mode direct I/O specification...
Page 39 3 PERFORMANCE SPECIFICATION MELSEC-Q Performance Specifications (continued) Model Item Remark Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Default 8192 points (M0 to 8191) Internal relay [M] Default 8192 points (L0 to 8191) Latch relay [L] Default 8192points (B0 to 1FFF) Link relay [B] Default 2048 points (T0 to 2047) (for low / high speed timer) Select between low / high speed timer by instructions.
Page 40 3 PERFORMANCE SPECIFICATION MELSEC-Q Performance Specifications (continued) Model Item Remark Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Link special relay [SB] 2048 points (SB0 to 7FF) Link special register [SW] 2048 points (SW0 to 7FF) Step relay [S] 8192 points (S0 to 8191) Index register [Z] 16 points (Z0 to 15) 4096 points (P0 to 4095), set parameter values to select usable range...
Page 41: Sequence Program Configuration And Execution Conditions
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS Sequence programs and SFC programs can be executed at the High Performance model QCPU. This chapter describes the sequence program configuration and execution conditions. SFC programs are not described in this manual. For details on SFC programs, refer to the QCPU (Q mode)/QnACPU Programming Manual (SFC).
Page 42 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (2) Sequence program writing format Programming for sequence programs is enabled using either ladder mode or list mode. Ladder mode • The ladder mode is based on the relay control sequence ladder. Programming expressions are similar to the relay control sequence ladder.
Page 43: Main Routine Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.1.1 Main routine program (1) Definition of main routine program A main routine program begins from step 0 and ends at the END/FEND instruction. In the main routine program, the instructions are executed from step 0 to the END/FEND.
Page 44: Sub-Routine Programs
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.1.2 Sub-routine programs (1) Definition of sub-routine program A sub-routine program begins from a pointer (P ) and ends at a RET instruction. A sub-routine program is executed only when called by a CALL instruction (e.g.
Page 45 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Using the sub-routine program as a separate program Sub-routine programs can also be managed as separate, separate programs (stand-by type programs). (See Section 4.2.4 for details on stand-by type programs). 4 - 5 4 - 5...
Page 46: Interrupt Programs
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.1.3 Interrupt programs (1) Definition of interrupt program An interrupt program begins from the interrupt pointer (I ), and ends at the IRET instruction. Interrupt programs are executed only when an interrupt factor occurs. POINT The interrupt pointers include a pointer designed for only the high speed interrupt function (I49).
Page 47 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Using the interrupt program as a separate program Interrupt programs can also be managed as separate, discrete programs (stand-by type programs). (See Section 4.2.4 for details on stand-by type programs). However, the same interrupt program pointer number cannot be used more than once in the program being executed by the CPU module.
Page 48 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Interruption during a network refresh: If an interrupt factor occurs during a network refresh operation, the network refresh operation is suspended, and the interrupt program is executed. This means that "assurance of blocks in cyclic data at each station" cannot be secured by using a device designated as a destination of link refresh operation on the MELSECNET/H Network System.
Page 49 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (5) Program creation restrictions A device which is switched ON by a PLS instruction in an interrupt program will remain ON until that interrupt program is executed again. PLS M0 PLS M0 IO IRET END 0 0 IO IRET END...
Page 50: Program Execute Type
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2 Program Execute Type Programs executed by High Performance model QCPU can be stored in the High Performance model QCPU's program memory, standard ROM or memory card. Programs can be stored in the standard ROM or memory card as a single program, but also as multiple programs by splitting them into separate programs for each control function.
Page 51 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (1) Execute Type Setting To execute several programs, specify a "Program name" and "Execute type" of each program at the "Program" tab screen in the “(PLC) Parameter" dialog box. High Performance model QCPU will execute the selected programs in the order of specified Execute Type setting.
Page 52 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q File Use Setting Sets whether to use the data (file register, initial device value, comment, local device) set at the “PLC file” tab screen in the “(PLC) Parameter” dialog box, per program. The data is set for each program. By default, the option "Use PLC file setting"...
Page 53 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (2) Flow of each program of High Performance model QCPU The flow of each program after power-ON or STOP of the PLC to RUN switching of the CPU module is shown below. Power ON/STOP to RUN Executed only once at power ON Initial execution...
Page 54 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (3) Changing the Execute Type The Execute Type setting made at the "Program" tab screen in the “(PLC) Parameter" dialog box can be changed at any time while a sequence program is executed. To change the execute type of a program, use a PSCAN, PLOW, PSTOP or POFF instruction.
Page 55: Initial Execution Type Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2.1 Initial execution type program (1) Definition of initial execution type program An initial execution type program is executed once only at power ON, or when STOP to RUN switching occurs. This program's execute type is designated as "initial" in the program of the PLC parameters.
Page 56 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (4) Initial scan time This is the execution time period for initial execution type programs. If multiple initial execution type programs are executed, it is the execution time period in which all those programs are executed. When an interrupt program/fixed scan execution type program is executed while an initial execution type program is running, the execution time of the interrupt program/fixed scan execution type program will be added to the...
Page 57: Scan Execution Type Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2.2 Scan execution type program (1) Definition of scan execution type program Scan execution type programs are executed once per scan, beginning from the scan which follows execution of the initial execution type program. Set the execute type to "scan"...
Page 58 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (5) Scan time The "scan time" is a total of following the execution time of the scan execution type program and END processing. If multiple scan execution type programs are used, the "scan time" is the total time required to execute all the programs.
Page 59: Low Speed Execution Type Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2.3 Low speed execution type program (1) Definition of low speed execution type program Low speed execution type programs are executed only during "constant scanning surplus time" or during the period designated for "low speed program execution time".
Page 60 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 1 If a constant scan time has been designated, the low speed execution type program will be executed repeatedly during the constant scan's surplus time. Therefore, the low speed execution type program's execution time varies from scan to scan.
Page 61 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 1 : Asynchronous method (1) Constant scan time setting The low speed execution type program is operated under the following conditions as shown below. • Constant scan time : 8ms • Total scan execution type program time : 4ms to 5ms •...
Page 62 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 2 : Synchronous method (1) Constant scan time setting The low speed execution type program is operated under the following conditions as shown below. • Constant scan time : 8ms • Total scan execution type program time : 4ms to 5ms •...
Page 63 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (4) Precautions for creating Low speed execution type programs See Section 10.6.1 for details on index register processing when switching from a scan execution type program to a low speed execution type program.
Page 64 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q The low speed scan time is measured by the High Performance model QCPU, and the result is stored in special registers (SD528 to SD535). The low speed scan time can therefore be checked by monitoring the SD528 to SD535 special registers.
Page 65: Stand-By Type Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2.4 Stand-by type program (1) Definition of stand-by type program Stand-by type programs are executed only when requested. Stand-by type programs are used for the following applications. Placing programs in the library Sub-routine and interrupt programs are converted to stand-by type programs which are managed separately from the main program.
Page 66 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Changing the program setup Create a program compatible with all programs and use it only to execute necessary programs. Programs designated as stand-by type programs in the “(PLC) Parameter" dialog box can be converted to scan execution type programs and executed in a sequence program.
Page 67 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q When changing the execute type of the scan execution type programs and stand-by type programs by the scan execution type programs having the condition for switching the execution type. • The scan execution type program being executed changes the next program to be executed from a stand-by type program to a scan execution type program.
Page 68 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q The execute type of program is switched at END processing. The program execute type does not change while the program is being executed. If different execute type is specified for a same program in a same scan, the last-specified execute type becomes effective.
Page 69 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (3) Precautions for creating stand-by type programs Because current value is updated and contact ON/OFF is switched when the OUT T instruction is executed, timers cannot be used in stand-by type programs. Gathering sub-routine programs in a single program Create the sub-routine programs in order beginning from step 0 of the stand-by type program.
Page 70 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Gathering interrupt programs in a single program Create the interrupt programs in order beginning from step 0 of the stand-by type program. An END instruction is required at the end of the interrupt program. Because there are no restrictions on the order of creating interrupt programs, the pointer numbers need not be assigned in ascending order when creating multiple interrupt programs.
Page 71: Fixed Scan Execution Type Program
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.2.5 Fixed scan execution type program (1) Definition of fixed scan execution type program This program is executed at specified intervals. Without describing an interrupt point and IRET instruction, a fixed scan execution can be performed for each file.
Page 72 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Execution during END processing: When the execution condition of fixed scan execution type programs are established during the wait time of END instruction while the constant scan is executed, the fixed scan execution type programs are executed. Perform the processing of the index register when the program is switched from the scan execution type program to the fixed scan execution type program by seeing Section 10.6.2.
Page 73 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (e) When the interrupt program/fixed scan execution type program is executed at a measuring time such as the scan time or execution time, the values of the interrupt program/fix scan execution type program are added to the measured time.
Page 74: Operation Processing
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.3 Operation Processing 4.3.1 Initial processing This is a preprocessing for sequence operation execution, and is performed only once as shown in the table below. When the initial processing is completed, the High Performance model QCPU goes in the RUN/STOP switch setting status.
Page 75: Automatic Refresh Of The Intelligent Function Module
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.3.3 Automatic refresh of the intelligent function module When automatic refresh of intelligent function modules is set, communication with the intelligent function modules of the designated data is performed. Refer to the manual of the intelligent function modules, for details on the automatic refresh setting of intelligent function modules.
Page 76: Run, Stop, Pause Operation Processing
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.4 RUN, STOP, PAUSE Operation Processing The High Performance model QCPU has three types of operation status; RUN, STOP and PAUSE status. The High Performance model QCPU operation processing is explained below: (1) RUN Status Operation Processing RUN status indicate that the sequence program operation is performed from step 0 to END (FEND) instruction to step 0 repeatedly.
Page 77: Operation Processing During Momentary Power Failure
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.5 Operation Processing during Momentary Power Failure The High Performance model QCPU detects a momentary power failure when the input power voltage supplied to the power supply module is lower than the regulated ranges.
Page 78: Data Clear Processing
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.6 Data Clear Processing (1) Data clear The High Performance model QCPU clears all data except for the following, when a reset operation is performed with RESET/L.CLR switch, or power ON to OFF to ON.
Page 79: I/O Processing And Response Lag
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.7 I/O Processing and Response Lag In the direct mode, the batch communication with I/O modules is performed before sequence program operation starts. By creating a sequence program with direct access I/O, I/O processing can be performed in a direct mode to communicate with I/O module at execution of each instruction in the sequence program.
Page 80 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q REMARK 1: The peripheral device input area can be switched ON and OFF by the following: • Test operation by the GX Developer • A network refresh by the MELSECNET/H network system •...
Page 81 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (2) Response lag An output module lags max.2 scans behind an input module. (See Fig.4.8) Ladder examples Ladder that turns the Y5E output ON when an X5 input turns ON. When Y5E turns ON fastest Input refresh Input refresh Output refresh...
Page 82: Direct Mode
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.7.2 Direct mode (1) Definition of direct mode In the direct mode the communication with the I/O modules is performed when executing sequence program instructions. With High Performance model QCPU, direct mode I/O processing can be performed by using direct access inputs (DX) and direct access outputs (DY).
Page 83 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (2) Response lag An output module lags max.1 scan behind an input module. (See Fig.4.10) Ladder examples Ladder that turns the DY5E output DY5E ON when an DX5 input turns ON. When DY5E turns ON fastest LD DX5 OUT DY5E 55 56...
Page 84: Numeric Values Which Can Be Used In Sequence Programs
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.8 Numeric Values which Can Be Used in Sequence Programs Numeric and alphabetic data are expressed by "0" (OFF) and "1" (ON) numerals in the High Performance model QCPU. This expression form is called "binary code" (BIN). The hexadecimal (HEX) expression form in which BIN data are expressed in 4-bit units, and the BCD (binary coded decimal) expression form are applicable to the High Performance model QCPU.
Page 85 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q (1) External numeric inputs to High Performance model QCPU When inputting numeric values to the High Performance model QCPU from an external source (such as digital switch), use BCD (binary coded decimal) which allows the same setting as decimal form.
Page 86: Bin (Binary Code)
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.8.1 BIN (Binary Code) (1) Binary code Binary date is represented by 0 (OFF) and 1 (ON). Decimal notation uses the numerals 0 through 9. When counting beyond 9, a 1 is placed in the 10s column and a 0 is placed in the 1s column to make the number In binary notation, the numerals 0 and 1 are used.
Page 87: Hex (Hexadecimal)
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.8.2 HEX (Hexadecimal) (1) Hexadecimal notation In hexadecimal notation, 4 binary bits are expressed in 1 digit. If 4 binary bits are used in binary notation, 16 different values from 0 to 15 can be represented.
Page 88: Bcd (Binary Coded Decimal)
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.8.3 BCD (Binary Coded Decimal) (1) BCD notation BCD notation is binary expression with a carry similar to that of the decimal notation. Though it uses 4-bit representation like hexadecimal notation, it dose not use letters A to F.
Page 89: Real Numbers (Floating Decimal Point Data)
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.8.4 Real numbers (floating decimal point data) (1) Real numbers Real numbers are single precision floating decimal point data. (2) Internal expression of floating decimal point data The High Performance model QCPU's internal expression of received real number data is explained below.
Page 90 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q Storing "0.75" (0.75) (0.11) (1.100..2 ) Mantissa code Positive to 0 Characteristic -1 to 7E to (01111110) Mantissa (100 00000 00000 00000 00000) Therefore, the data expression will be 3F400000 , as shown below. Code Characteristic Mantissa...
Page 91 4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q REMARK In binary notation, the portion of the value following the decimal point is calculated as follows: This bit expresses 2 This bit expresses 2 This bit expresses 2 This bit expresses 2 (0.1101) = 0.5 + 0.25 + 0.0625 = (0.8125) 4 - 51...
Page 92: Character String Data
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS MELSEC-Q 4.9 Character String Data (1) Character String Data The High Performance model QCPU uses ASCII code data. (2) ASCII code character strings ASCII code character strings are shown in the Table below. "00 "...
Page 93: Assignment Of I/O Numbers
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5 ASSIGNMENT OF I/O NUMBERS This section describes the necessary information on the I/O number assignment for the data exchange between High Performance model QCPU and I/O modules or intelligent function modules. 5.1 Relationship Between the Number of Stages and Slots of the Extension Base Unit High Performance model QCPU allows the system configuration using eight base units: one main base unit and seven extension base units.
Page 94: Installing Extension Base Units And Setting The Number Of Stages
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.2 Installing Extension Base Units and Setting the Number of Stages There are two types of extension base units: Q5 B/ Q6 B for mounting of Q-Series modules and QA1S6 B and for mounting AnS Series modules. (1) Connecting order of extension base units When using both Q5 B/ Q6 B and QA1S6 B, connect all Q5 B/ Q6 B modules closer to the main base unit, then connect QA1S6 B modules.
Page 95: Base Unit Assignment (Base Mode)
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.3 Base Unit Assignment (Base Mode) There are "Auto" and "Detail" modes to assign the number of modules can be mounted in the main and extension base units of High Performance model QCPU. (1) Auto mode In Auto mode, the slot numbers are assigned to the main and extension base units according to the number of slots than can be occupied.
Page 96 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q For 8-slot base unit: 8 slots are occupied Q38B type main base unit Q68B type extension base unit 9 10 11 12 13 14 15 For 12-slot base unit: 12 slots are occupied Q312B type main base unit 9 10 11 Q612B type extension base unit 12 13 14 15 16 17 18 19 20 21 22 23...
Page 97 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q (2) Detail mode In Detail mode, the number of mountable modules is assigned to the individual base units (main and extension base units) at the "I/O assignment" tab screen in the “(PLC) Parameter" dialog box. Use this mode to match the number of slots to the one for the AnS Series base units (8 fixation).
Page 98 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q (3) Setting screen and setting items for Base mode of GX Developer Base model name Designate the model name of the installed base unit with 16 or less characters. High Performance model QCPU does not use the designated model name.
Page 99: What Are I/O Numbers
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.4 What are I/O Numbers? I/O numbers are used in sequence programs for importing ON/OFF data to High Performance model QCPU from outsides and outputting ON/OFF data from High Performance model QCPU to outsides. Input (X) is used for the importing of ON/OFF data to High Performance model QCPU.
Page 100: Concept Of I/O Number Assignment
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.5 Concept of I/O Number Assignment 5.5.1 I/O numbers of main base unit and extension base unit High Performance model QCPU assigns I/O numbers at power-on or reset according to the following items. As a result, High Performance model QCPU can be controlled without performing I/O assignment using GX Developer.
Page 101 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q The following shows the example of the I/O number assignment when the base unit is set in Auto mode without I/O assignment: Q35B (5 slots occupied) ..... Slot No. Allocate the I/O number with the I/O points of each slot points points...
Page 102: Remote Station I/O Number
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.5.2 Remote station I/O number It is possible to allocate High Performance model QCPU device input (X) and output (Y) to remote station I/O modules and intelligent function modules and control the modules in the MELSECNET/H remote network, the CC-Link and other remote I/O systems.
Page 103: I/O Assignment By Gx Developer
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.6 I/O Assignment by GX Developer This section describes the I/O assignment using GX Developer. 5.6.1 Purpose of I/O assignment by GX Developer I/O assignment by GX Developer is used under the following circumstances. (1) Reserving points when converting to module other than 16-point modules You can reserve the number of points in advance so that you do not have to...
Page 104: Concept Of I/O Assignment Using Gx Developer
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.6.2 Concept of I/O assignment using GX Developer (1) I/O assignment for each slot "Type" (module type), "Points" (number of occupied I/O points), and "Start" (head I/O number) can be designated individually for each slot of the base unit. For example, to change the number of occupied I/O points of the designated slot, only the number of occupied I/O points can be designated.
Page 105 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q Model name Designate the model name of the mounted module with 16 or less characters. High Performance model QCPU does not use the designated model name. (It is used as a user's memo) Points (Used with High Performance model QCPU) To change the number of occupied I/O points of each slot, select it from the followings: •...
Page 106 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q Be sure to set the same module type for the mounted module and the I/O assignment. If the module type of the I/O assignment is different from that of the actually mounted module, the module may not work normally. For the intelligent function module, make sure that the numbers of I/O points are the same.
Page 107: Examples Of I/O Number Assignment
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q 5.7 Examples of I/O Number Assignment This section shows the examples of the I/O number assignment using GX Developer. (1) When changing the number of points of an empty slot from 16 to 32 points: Reserve 32 points to the empty slot (slot No.
Page 108 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q I/O assignment with GX Developer Designate slot No. 3 to "32 points" at the "I/O assignment" tab screen of GX Developer. Select 32 points. (When the type is not selected, the type of the installed module will be selected.) I/O number assignment after the I/O assignment with GX Developer Q38B...
Page 109 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q (2) Changing the I/O number of slots Change the I/O number of an empty slot (slot No. 3) to X200 through X21F so that the I/O numbers of slot No. 4 and later slots do not change when a 32-point input module is mounted to the empty slot (slot No.
Page 110: Checking The I/O Numbers
5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q I/O assignment with GX Developer Designate the head I/O number of slot No. 3 to "200" and that of slot No. 4 to "70" at the "I/O assignment" tab screen of GX Developer. "200" is designated as the head I/O number.
Page 111 5 ASSIGNMENT OF I/O NUMBERS MELSEC-Q MEMO 5 - 19 5 - 19...
Page 112: High Performance Model Qcpu Files
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6 HIGH PERFORMANCE MODEL QCPU FILES (1) High Performance model QCPU file type The High Performance model QCPU parameters, programs, comment data, etc. are assigned "file names" and "extension", and are then stored in the following memories: •...
Page 113 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (4) File details File name, file size and writing date, which are set when created with GX Developer, are added to every file written into High Performance model QCPU. When monitoring the files by GX Developer, the files are displayed as shown below.
Page 114: About The High Performance Model Qcpu's Memory
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.1 About the High Performance model QCPU's Memory (1) User Memory A user memory can be created within the memory of the High Performance model QCPU by using the GX Developer/sequence program. The High Performance model QCPU has the following built-in memories: •...
Page 115 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (2) Types of Data Stored in the High Performance model QCPU Memory or on the Memory Card The table below shows the type of data stored in a standard RAM/standard ROM or on a memory card. High Performance model Memory Memory Card (ROM)
Page 116 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (3) Drive Number The High Performance model QCPU uses drive numbers to control standard RAMs, standard ROMs, and memory cards. GX Developer specifies a selected memory (standard RAM, standard ROM or memory card) to read/write parameters and program files from to the High Performance model QCPU.
Page 117: Program Memory
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.2 Program Memory (1) What is the Program Memory? The High Performance model QCPU's program memory is an internal RAM that stores programs executed by the High Performance model QCPU. The data storage in the program memory is backed up by High Performance model QCPU's built-in batteries (Q6BAT).
Page 118 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q Memory capacity after formatting The memory capacity of the program memory after formatting is as follows. Table 6.1 Memory capacity after formatting Memory Model Name Max. Number of Files Stored Q02CPU 28 k steps (114688 bytes) 28 files Q02HCPU 28 k steps (114688 bytes)
Page 119: About The Standard Rom
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.3 About the Standard ROM (1) What is the standard ROM? The standard ROM is used for the ROM operation of the High Performance model QCPU. Programs stored in the standard ROM can be used after being read (boosted) to the program memory in accordance with the setting made at the "Boot file"...
Page 120: About The Standard Ram
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.4 About the Standard RAM (1) What is the standard RAM? The standard RAM is used when using file registers or local devices without a memory card being mounted on the High Performance model QCPU. The standard ROM must be formatted by using GX Developer when using the High Performance module QCPU for the first time.
Page 121 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (4) Precautions When setting file registers and local devices in the standard RAM, memory capacity is secured in 1024 byte units for the Q12HCPU/Q25HCPU that have the serial number whose upper five digits are “02092” or later. Memory capacity is secured in 512 byte units for the Q12HCPU/Q25HCPU, Q02CPU, Q02HCPU and Q06HCPU that have the serial number whose upper five digits are "02091"...
Page 122: Memory Card
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.5 Memory Card (1) Memory card A memory card is used to expand the size of an internal memory of the High Performance model QCPU. There are three types of memory cards for use in the High Performance model QCPU: SRAM card, Flash card, and ATA card.
Page 123: Writing Data To The Standard Rom Or The Flash Card
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.6 Writing Data to the Standard ROM or the Flash Card 6.6.1 Writing Data to the standard ROM or to the Flash card using GX Developer The "write to PLC" function in the GX Developer Online menu does not allow the user to write files into a standard ROM or on a Flash card.
Page 124 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (d) When the "Write to PLC (Flash ROM)" function is executed, all files stored in the standard ROM or on the Flash card are erased before a batch of files specified by GX Developer are written. No files can be added to the standard ROM or Flash card.
Page 125: Automatic Write To Standard Rom (Auto Download All Data From Memory Card To Standard Rom)
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.6.2 Automatic write to standard ROM (Auto Download all Data from Memory card to Standard ROM) "Automatic write to standard ROM" function writes the parameters and sequence programs stored on the memory card into the High Performance model QCPU's standard ROM without using GX Developer.
Page 126 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (1) Execution procedure for "Automatic write to standard ROM" Observe the following procedure for "Automatic write to standard ROM". Operations with the GX Developer (Settings for "Automatic write to Standard ROM") Check "Auto Download all Data from Memory card to Standard ROM"at the "Boot file"...
Page 127 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (2) Precautions This section indicates the precautions for performing "Automatic write to standard ROM" If the file to be booted from the memory card shares the same name as a file in the program memory, the memory card data will be overwritten. Also, if the file to be booted from the memory card does not share the same name as a file in the program memory, it will be added to the program memory.
Page 128: Executing Standard Rom/Memory Card Programs (Boot Run)
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.7 Executing Standard ROM/Memory Card Programs (Boot Run) (1) Executing High Performance model QCPU programs The High Performance model QCPU executes programs stored in the program memory. The High Performance model QCPU does not perform operation of programs stored in the standard ROM or memory cards.
Page 129 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q (3) Changing Program Files While the High Performance model QCPU is in the Run Status. (a) While the High Performance model QCPU is in RUN status, addition/change/deletion of program files from the standard ROM or memory card to the program memory can be made by using any of the following instructions in a sequence program.
Page 130 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q If the program memory is changed when a sequence program is written in the program memory and PLC is turned on or reset, boot operation mode may be selected. If the "BOOT" LED is lit on the front panel of the High Performance model QCPU, the boot operation mode is selected.
Page 131: Program File Configuration
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.8 Program File Configuration (1) Program File Configuration Program files consist of a file header, an execution program, and allocate memory allocated for "Write during RUN". Program file configuration 34 steps File header (default) Execution program The area is allocated in 1k steps.
Page 132 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q PRECAUTIONS 1) The program capacity displayed during programming with GX Developer is the sum of file header and executed program capacities and does not include the capacity of steps secured for write during RUN. 2) Since a file is stored on the program memory in 1k step units, the program capacity displayed during programming with GX Developer may differ from the capacity of the program file on the High Performance model QCPU.
Page 133: Gx Developer File Operation And File Handling Precautions
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.9 GX Developer File Operation and File Handling Precautions 6.9.1 File operation GX Developer online operation allows the files which are stored in the program memory, standard ROM and memory card, to perform the file operations in the table below.
Page 134: File Handling Precautions
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.9.2 File handling precautions (1) Power OFF (or reset) during program operation If power is switched OFF during a file operation which will not cause a file shift, the memory data will not be lost. If files and data in the memory of the High Performance model QCPU is backed up using the battery (Q6BAT), the program memory data will not be lost when the power is switched OFF during the following file operations...
Page 135: File Size
6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q 6.9.3 File size The file size differs with the types of files used. When a program memory, standard RAM, standard ROM, and memory card are used, calculate the size of a file by referring to the table 6.7 shown below.
Page 136 6 HIGH PERFORMANCE MODEL QCPU FILES MELSEC-Q An example for calculating the amount of memory capacity required when writing the parameters and sequence programs in the program memory is shown below. (1) Writing file File name Program capacity PARAM.QPA (parameter) —...
Page 137: Function
7 FUNCTION MELSEC-Q 7 FUNCTION Function of High Performance model QCPU module is as follows: 7.1 Function List Functions of High Performance model QCPU are listed below: Item Description Reference section Constant scan This function executes the program in a set time interval regardless of the program scan time. Section 7.2 Latch function This function maintains the device data when performing the reset operation during power off.
Page 138: Constant Scan
7 FUNCTION MELSEC-Q 7.2 Constant Scan (1) What is Constant Scan? The scan time differs because the processing time differs depending on whether the instruction, which is used in the sequence program, is executed or not. Constant scan is a function to execute the sequence program repeatedly while maintaining the scan time at a constant time.
Page 139 7 FUNCTION MELSEC-Q (2) Setting the constant scan time The constant scan time is set at the "PLC RAS" tab screen in the “(PLC) Parameter" dialog box. The constant scan can be set in the range of 0.5 ms to 2000 ms. A setting can be made in 0.5 ms units.
Page 140 7 FUNCTION MELSEC-Q The sequence program processing stops during the wait time from the last END processing execution until the next scan starts. If a low speed execution type program is executed, it will be interrupted for - 0.5 ms (a constant scan time setting). If an interrupt factor occurs after the END processing is performed, the interrupt program or fixed scan execution type program is executed.
Page 141: Latch Functions
7 FUNCTION MELSEC-Q 7.3 Latch Functions (1) What is Latch Functions? The values of each High Performance model QCPU device are set back to the default (bit device: OFF and word device: 0) when; • The PLC power is turned on. •...
Page 142 7 FUNCTION MELSEC-Q Clearing the Latch Range Device Data The status of devices to which "latch clear" is made is shown in the table below. Latch setting Clear/retention after "latch clear" Devices not designated in latch range Clear Latch (1) setting (Devices with "latch clear" option) Clear Latch (2) setting (Devices without "latch clear"...
Page 143: Setting The Output (Y) Status When Changing From/To Stop Status To/From Run Status
7 FUNCTION MELSEC-Q 7.4 Setting the Output (Y) Status when Changing from/to STOP Status to/from RUN Status (1) Output (Y) Status when changing from STOP Status to RUN Status When changing from RUN status to STOP status, the RUN status output (Y) is stored in the sequence and all the outputs (Y) are turned OFF.
Page 144 7 FUNCTION MELSEC-Q (2) Setting the Output (Y) Status when Changing from STOP Status to RUN Status The output (Y) status before the STOP status when switching from STOP status to Run status can be set at the "PLC System" tab screen in the “(PLC) Parameter"...
Page 145: Clock Function
7 FUNCTION MELSEC-Q 7.5 Clock Function (1) What is Clock Function? Clock function reads the clock data inside the High Performance model QCPU with a sequence program and uses the data for clock management. Also, the time data is used for time maintenance for the High Performance model QCPU system functions such as those for failure history.
Page 146 7 FUNCTION MELSEC-Q Method to Write from the Program The time data is written to the clock element by using the clock instruction (DATEWR). A program example to write the time data using the time data write instruction (DATEWR). Write request MOVP K1999 Year 1999...
Page 147 7 FUNCTION MELSEC-Q (3) Precautions The clock data is not set prior to shipment. The clock data is used in High Performance model QCPU system and intelligent function module for failure history and other functions. Be sure to set the accurate time when operating the High Performance model QCPU for the first time.
Page 148: Remote Operation
7 FUNCTION MELSEC-Q 7.6 Remote Operation The High Performance model QCPU provides the RUN/STOP switches for switching between the STOP status and the RUN status. The RESET/L.CLR switch also provides the Reset and Latch Clear functions. The High Performance model QCPU can allow control of the High Performance model QCPU operation status by external operations (GX Developer function, intelligent function module, and remote contact).
Page 149 7 FUNCTION MELSEC-Q (2) Method with Remote RUN/STOP There are two ways to perform remote RUN/STOP: Method with remote RUN contact The remote RUN contact is set at the "PLC system" tab screen in the “(PLC) Parameter" dialog box of GX Developer. The device can be set in the range of input X0 to 1FFF.
Page 150 7 FUNCTION MELSEC-Q (3) Precautions Take note of the following, because STOP has priority in High Performance model QCPU: The High Performance model QCPU enters the STOP status when remote STOP is performed from remote RUN contact, GX Developer, or by using serial communication module. To set the High Performance model QCPU to RUN status from STOP status again, perform the remote RUN from the external factor (remote RUN contact, GX Developer, serial communication module, etc.) from...
Page 151: Remote Pause
7 FUNCTION MELSEC-Q 7.6.2 Remote PAUSE (1) What is Remote PAUSE? The remote PAUSE performs PAUSE of the High Performance model QCPU externally with the CPU module RUN/STOP switch at RUN position. The PAUSE function stops the High Performance model QCPU calculations while maintaining the ON/OFF status of all output (Y).
Page 152 7 FUNCTION MELSEC-Q Method with GX Developer, Serial Communication Module etc. The remote PAUSE operation can be performed from the GX Developer or by using serial communication module. The GX Developer operation is performed by on-line remote operation. The serial communication module and Ethernet interface module are controlled by commands complying with the MC protocol.
Page 153: Remote Reset
7 FUNCTION MELSEC-Q 7.6.3 Remote RESET (1) What is Remote RESET? The remote RESET resets the High Performance model QCPU externally when the High Performance model QCPU is at STOP status. Even if the High Performance model QCPU RUN/STOP switch is at RUN, the reset can be performed when the High Performance model QCPU is stopped and an error that can be detected by the self-diagnosis function occurs.
Page 154 7 FUNCTION MELSEC-Q (3) Precautions To perform the remote RESET, check the "Allow" check box of the "Remote reset" section at the "PLC system" tab screen in the “(PLC) Parameter" dialog box, and then write parameters into High Performance model QCPU. If the "Allow"...
Page 155: Remote Latch Clear
7 FUNCTION MELSEC-Q 7.6.4 Remote latch clear (1) What is Remote Latch Clear? The remote latch clear resets the device data latched to the High Performance model QCPU using the GX Developer etc., when the High Performance model QCPU is in STOP status. Remote latch clear is useful when the High Performance model QCPU is in the following areas.
Page 156: Relationship Of The Remote Operation And High Performance Model Qcpu Run/Stop Switch
7 FUNCTION MELSEC-Q 7.6.5 Relationship of the remote operation and High Performance model QCPU RUN/STOP switch (1) Relationship of the Remote Operation and High Performance model QCPU Switch The High Performance model QCPU operation status is as follows with the combination of remote operations to RUN/STOP switch.
Page 157: Selecting The Response Time Of The Input Module
7 FUNCTION MELSEC-Q 7.7 Selecting the Response Speed of the Q Series Module (I/O Response Time) 7.7.1 Selecting the response time of the input module (1) Selecting the response time of the input module The input response time of a Q Series input module can be set to a desired response time: 1 ms, 5 ms, 10 ms, 20 ms or 70 ms.
Page 158: Selecting The Response Time Of The High Speed Input Module
7 FUNCTION MELSEC-Q 7.7.2 Selecting the response time of the high speed input module (1) Selecting the response time of the high speed input module Changing the response time of the high speed input module means to amend the input response speed for high speed input modules (QX40-S1) that support the Q Series to 0.1 ms, 0.2 ms, 0.4 ms, 0.6 ms and 1 ms.
Page 159: Selecting The Response Time Of The Interrupt Module
7 FUNCTION MELSEC-Q 7.7.3 Selecting the response time of the interrupt module (1) Selecting the response time of the interrupt module Changing the response time of the interrupt module means to amend the input response speed for interrupt modules (QI60) that support the Q Series to 0.1 ms, 0.2 ms, 0.4 ms, 0.6 ms and 1 ms.
Page 160: Setting The Switches Of The Intelligent Function Module
7 FUNCTION MELSEC-Q 7.8 Setting the Switches of the Intelligent Function Module (1) Setting the Switches of the Intelligent Function Module The switches of the intelligent function module is to set the switches of an Q Series intelligent function module using GX Developer. The settings of the switches set by GX Developer is written from High Performance model QCPU to each intelligent function module at the leading edge or reset of High Performance model QCPU.
Page 161: Monitoring Function
7 FUNCTION MELSEC-Q 7.9 Monitoring Function (1) What is Monitoring Function? This is a function to read the program, device and intellignet function module status of the High Performance model QCPU by using GX Developer. The High Performance model QCPU performs the END processing to handle monitor requests from GX Developer.
Page 162 7 FUNCTION MELSEC-Q POINT If a step between the AND/OR blocks is specified as a monitor condition, monitor data is sampled when the status previous to execution of the specified step is specified by the LD instruction. The monitor timing depends on the step specified as a monitor condition.
Page 163 7 FUNCTION MELSEC-Q POINT When "Step No.[100]=<-P->, Word Device [D1]=[K5]" is specified as the detailed condition in the following circuit, a monitor execution condition is established at the leading edge of the 100th step where D1=5. 100th step INC D1 The monitor interval of GX Developer depends on the processing speed of GX Developer.
Page 164 7 FUNCTION MELSEC-Q (b) When "Device" is specified: "Word Device" or "Bit Device" can be specified. When "Word Device " is selected: The monitoring operation is stopped when the current value of the specified word device becomes the specified value. A current value can be expressed in decimal digits, hexadecimal digits, 16-bit integral numbers, 32-bit integral numbers, or real numbers.
Page 165: Monitoring Test For Local Device
7 FUNCTION MELSEC-Q 7.9.2 Monitoring test for local device (1) Monitoring and Testing Local Devices Local devices specified at the "Device" tab screen in the “(PLC) Parameter" dialog box can be monitored or tested by operating from GX Developer. This function is useful when debugging a program and monitoring local devices in a program monitored by GX Developer.
Page 166 7 FUNCTION MELSEC-Q (2) Monitoring the Local Devices Monitor local devices in the following steps: Connect the personral computer to the CPU module. Display the circuit in the circuit mode. Change the mode to the monitor mode. Select "Tool". Select "Option". Display option window Select "Program type".
Page 167: Enforced On/Off For External I/O
7 FUNCTION MELSEC-Q 7.9.3 Enforced ON/OFF for external I/O Enforced ON/OFF operations from GX Developer will forcibly switch the external I/O on and off. The information registered for ON/OFF will be cancelled with GX Developer operations. A GX Developer Version 6 or higher is required to use this function. It is possible to perform enforced ON (enforced ON registration,) enforced OFF (enforced OFF registration) and cancel enforced ON/OFF (cancel registration) with the enforced ON/OFF function.
Page 168 7 FUNCTION MELSEC-Q The input and output eligible for enforced ON/OFF are shown below. Input (X) and output (Y) for modules mounted on the base unit. I/O (X/Y) of High Performance model QCPU or I/O (LX/LY) of MELSECNET/H modules to be refreshed High Performance model QCPU.
Page 169 7 FUNCTION MELSEC-Q The timing for external I/O enforced ON/OFF is shown in the table below. Refresh area Input Output • During END processing (input • During END processing (output refresh) refresh) • During the execution of • During the execution of I/O modules on the commands that used direct commands that used direct...
Page 170 7 FUNCTION MELSEC-Q (2) Operation procedure The operation procedure is explained below. Register enforced ON/OFF for the specified device. [Online] [Debug] [Enforced I/O Registration/Cancellation] It is possible to perform enforced ON or enforced OFF for a specified device by selecting [Enforced ON Registration] or [Enforced OFF Registration] after the device has been specified on the [Enforced I/O Registration/Cancellation] setup screen.
Page 171: Writing In Program During High Performance Model Qcpu Run
7 FUNCTION MELSEC-Q 7.10 Writing in Program during High Performance model QCPU RUN When the High Performance model QCPU is in the RUN status, you can write programs or files in any of the following steps: • Writing data in the circuit mode during RUN. •...
Page 172 7 FUNCTION MELSEC-Q (2) Precautions Take a note of the following when writing during RUN: The memory that can be written during RUN is only program memory. If the write during RUN is performed while booting a program from a memory card (RAM), the program to be booted will be changed.
Page 173 7 FUNCTION MELSEC-Q The capacity of a High Performance model QCPU's program file is a sum of the capacity of the program created and steps used for the write during RUN. The write during RUN is executed when the capacity of a program file is increased.
Page 174: Writing A Batch Of Files During Run
7 FUNCTION MELSEC-Q 7.10.2 Writing a batch of files during RUN (1) File-Write During RUN function The file-write during RUN function is used to write a batch of files to the High Performance model QCPU as shown below in the table. High Performance model QCPU Built-in Memory Card (RAM) Memory Card (ROM) Memory Name...
Page 175 7 FUNCTION MELSEC-Q (2) Precautions The precautions for file-write during RUN are as follows. The file-write during RUN can be executed when any of the following conditions is met. A SFC program does not allow writing a batch of files during the RUN status.
Page 176: Execution Time Measurement
7 FUNCTION MELSEC-Q 7.11 Execution Time Measurement This is a function to display the processing time of the program being executed. This is used to find out the effect of each program's processing time on the total scan time. There are three functions to the execution time measurement. The details of each function are indicated in sections 7.11.1 to 7.11.3.
Page 177 7 FUNCTION MELSEC-Q "Total Scan Time" The monitor time set in WDT(the watch dog timer) of "PLC RAS" tab screen in the (PLC) "Parameter" dialog box and total scan time for each program type are displayed. "Monitor Time" The monitoring time for the scan execution type program, initialization program, and low speed execution type program are displayed.
Page 178 7 FUNCTION MELSEC-Q (3) Program can be started and stopped on the program list monitor screen. Startup program button Clicking the startup program button displays the following dialog box. Program name Only the program, that is set at the "Program" tab screen in “(PLC) Parameter"...
Page 179 7 FUNCTION MELSEC-Q Stop program button Clicking the stop program button displays the following dialog box. Program name Only the program, that is set at the <Program> tab in the “(PLC) Parameter" dialog box, can be selected. It is not allowed to enter a program name freely. Stop mode •...
Page 180: Interrupt Program Monitor List
7 FUNCTION MELSEC-Q 7.11.2 Interrupt program monitor list (1) What is Interrupt Program Monitor List? This function displays execution count of the interrupt program (I0 to I255). This is used to confirm the execution status of the interrupt program. (2) Using the Interrupt Program Monitor List Choose "Online"...
Page 181: Scan Time Measurement
7 FUNCTION MELSEC-Q 7.11.3 Scan time measurement (1) What is Scan Time Measurement? This function displays the set program interval processing time. To specify a scan time measurement range, follow either of the following two steps: • Make the setting on the "Ladder monitor" window. •...
Page 182 7 FUNCTION MELSEC-Q The scan time measurement range is specified. (The specified area is highlighted.) Choose "Online" "Monitor" "Scantime measurement" to open "Scan time Measurement" dialog box. Click on the "Start" button. Precautions Set the "Measurement limit" so that the value of "Start step" is larger than that of "End step".
Page 183: Sampling Trace Function
7 FUNCTION MELSEC-Q 7.12 Sampling Trace Function POINT (1) The SRAM card (Q2MEM-1MBS, Q2MEM-2MBS) is required to store the trace data and trace results. After mounting the SRAM card to the High Performance model QCPU, execute sampling trace. (2) Sampling trace is not executed if the Flash card (Q2MEM-2MBF, Q2MEM- 4MBF) or ATA card (Q2MEM-8MBA, Q2MEM-16MBA, Q2MEM-32MBA) is installed, because the cards cannot store the trace data and trace results.
Page 184 7 FUNCTION MELSEC-Q The trace result displays the ON/OFF status of the bit device for the sampling cycle, and the current value of the word device. POINT Device details are read under trigger conditions specified in the trigger point setting. Sampling is performed for each scan.
Page 185 7 FUNCTION MELSEC-Q The execution status of the sampling trace function is stored in the special relay (SM800, SM802, SM804 and SM805). If an error occurs while the sampling trace function is used, SM826 turns on. By using special relays in a sequence program, the execution status of the sampling trace function can be checked.
Page 186 7 FUNCTION MELSEC-Q Trace interrupt When SM801 (sampling trace start) is turned off during sampling trace, the sampling trace is interrupted. In the meantime, the number of traces is cleared. When turning on SM801 again, trace is restarted. SM801 SM801 Trace Trigger Trigger...
Page 187 7 FUNCTION MELSEC-Q (2) Operation Procedure The sampling trace operation is performed in the following procedures: Each operation is performed on the "Sampling trace" dialog box within the online mode trace menu. Trace Device Setting Set the device to perform sampling trace at the "Trace data" tab screen in the "Sampling trace"...
Page 188 7 FUNCTION MELSEC-Q Setting the Trace Condition Set the trace condition at the "Conditions" tab screen in the "Sampling trace" dialog box. The trace condition setting can set to "No. of traces", "Trace point setup", "Trigger point setup", and "Additional trace information". No.
Page 189 7 FUNCTION MELSEC-Q Trace Point Setup This sets the timing to collect trace data. Select one from the following: a) Each Scan Collects trace data for every scan (END processing). b) Interval Collects trace data at specified times. c) Detailed Sets the device and step no.
Page 190 7 FUNCTION MELSEC-Q The created trace data and trace condition is written to the memory card. The trace file is written to the memory card (SRAM card). The trace file is written to the memory card (SRAM card) from the "Write to PLC"...
Page 191 7 FUNCTION MELSEC-Q At the "Trace Condition" section, select one of the following: • Execute by overwriting the conditions on PLC side. Overwrites trace condition to the existing trace file. • Execute by following conditions written on PLC side Executes the program with the conditions in the trace file specified in "Trace Data (Condition + Results) storing dest".
Page 192: Debug Function With Multiple Users
7 FUNCTION MELSEC-Q 7.13 Debug Function with Multiple Users (1) What is Debug Function with Multiple Users? This function performs debugging from multiple GX Developer connected to High Performance model QCPU or Serial communication module at the same time. If debugging tasks are classified by process or by function, this function is used to perform debugging of different files from multiple GX Developer at once.
Page 193: Multiple-User Monitoring Function
7 FUNCTION MELSEC-Q 7.13.1 Multiple-user monitoring function (1) What is Multiple-User Monitoring Function? The multiple-user monitoring operation can be performed by operating from multiple GX Developers connected to the High Performance model QCPU or the Serial communications module. Multiple users can monitor at the same time. By setting a station monitor file, high speed monitoring can be performed.
Page 194: Multiple-User Run Write Function
7 FUNCTION MELSEC-Q 7.13.2 Multiple-user RUN write function (1) What is Multiple-User RUN Write Function? Multiple users can write to one file or different files during RUN. To enable multiple users to write to a single file at the same time during RUN operation, specify the desired pointer for the "write during RUN"...
Page 195 7 FUNCTION MELSEC-Q The specified circuit of the pointer is displayed to write the circuit after conversion during RUN. The following is an example of GX Developer A writing during RUN from P0 and GX Developer B writing during RUN from P1. The program area surrounded with is the area to be written during RUN.
Page 196: Watch Dog Timer (Wdt)
7 FUNCTION MELSEC-Q 7.14 Watch dog Timer (WDT) (1) What is Watch dog Timer (WDT)? The watch dog timer is an internal sequence timer to detect High Performance model QCPU hardware and sequence program error. (b) When the watch dog timer expires, a watch dog timer error occurs. The High Performance model QCPU responds to the watch dog timer error as follows: The High Performance model QCPU turns off all outputs.
Page 197 7 FUNCTION MELSEC-Q The scan time value is not reset even if the watch dog timer is reset in the sequence program. The scan time value is measured to the END instruction. Internal processing time Sequence program Internal processing time Low speed execution type Low speed execution type program C...
Page 198: Self-Diagnosis Function
7 FUNCTION MELSEC-Q 7.15 Self-Diagnosis Function (1) What is Self-Diagnosis Function The self-diagnosis is a function performed by the High Performance model QCPU itself to diagnose whether there is an error in the High Performance model QCPU. The self-diagnosis function is used to prevent the High Performance model QCPU erroneous operation as well as preventive maintenance.
Page 199 7 FUNCTION MELSEC-Q (4) Error check selection The following error checking can be set to "yes/no" at the "PLC RAS" tab screen in the “(PLC) Parameter" dialog box. (All parameter defaults are set at "Yes".) Battery check Fuse blown check I/O unit comparison Self-Diagnosis List Diagnosis description...
Page 200 7 FUNCTION MELSEC-Q Self-Diagnosis List (Continued from the preceding page) Diagnosis description Error message Diagnostic timing • When the power is turned on/when reset Password error REMOTE PASS.ERR. • When switched from STOP to RUN • When the power is turned on/when reset Instruction code check INSTRUCT CODE.ERR.
Page 201: Interrupt Due To Error Occurrence
7 FUNCTION MELSEC-Q 7.15.1 Interrupt due to error occurrence The High Performance model QCPU can execute the interrupt program of the interrupt pointer that is set as the interrupt object when an error occurs. Only when the error set to "continue" at the "PLC RAS" tab screen in the “(PLC) Parameter"...
Page 202: Error Caucellation
7 FUNCTION MELSEC-Q 7.15.3 Error cancellation High Performance model QCPU error cancel operation can be performed only for error that can continue the High Performance model QCPU operation. Error cancellation Procedures for error cancellation The error cancel is performed as follows: Resolve the cause of error.
Page 203: Failure History
7 FUNCTION MELSEC-Q 7.16 Failure History The High Performance model QCPU can store the failure history (results detected from the self-diagnosis function and the time) in the memory. POINT The detection time uses the High Performance model QCPU internal clock, so make sure to set the correct time when using the High Performance model QCPU for the first time.
Page 204: System Protect
7 FUNCTION MELSEC-Q 7.17 System Protect The High Performance model QCPU has a few protection functions (system protect) to prevent the program changes by a third party other than the designer (from GX Developer function or serial communication module). There are the following methods for system protects. Valid Item to protect Protect valid file...
Page 205 7 FUNCTION MELSEC-Q (1) Password Registration To register the password, select GX Developer Online Password setup/keyword set up for writing to PLC Register password. Each item is described below: Target memory ....Specifies the memory storing the file whose password is to be registered or changed. Data type......Displays the type of a file stored in the target memory.
Page 206 7 FUNCTION MELSEC-Q 7.17.2 Remote passwords The remote password function prevents illegal access to the High Performance model QCPU by users in remote locations. The remote password function is enabled for use by setting it up in the High Performance model QCPU. When the remote password function has been set, a check will be run on remote passwords when users in remote locations attempt to access the High Performance model QCPU with serial communication modules or Ethernet modules with modem...
Page 207 7 FUNCTION MELSEC-Q (2) Remote password lock/unlock processing Unlocks the Ethernet module remote passwords for the access source via modems, serial communication modules and the Ethernet. Access to the High Performance model QCPU is enabled if the remote password matches up. For example, an outline of what will happen during remote password lock/unlock processing with an Ethernet module is shown below.
Page 208: Remote Password
7 FUNCTION MELSEC-Q (3) Procedure for setting up the remote password [GX Developer] [Remote Password] [Remote Password Setup] screen [Advanced Remote Password Setup] screen. Setup screen Remote password setup Detail is required with the QJ71E71 Setup fields Field Description Setup range/Selection range Password settings Remote password entry 4 bytes, alphanumerics, special characters...
Page 209: Monitoring High Performance Model Qcpu System Status From Gx Developer (System Monitor)
7 FUNCTION MELSEC-Q 7.18 Monitoring High Performance model QCPU System Status from GX Developer (System Monitor) In Case of GX Developer Version 4 (SW4D5C-GPPW-E) or GX Developer Version 5 (SW5D5C-GPPW-E) The System Monitor window provides the following information about the High Performance model QCPU connected to the personal computer: •...
Page 210 7 FUNCTION MELSEC-Q Parameter status The "Parameter status" section shows the I/O number of each slot of a base unit, module type, and the number of points. If the number of available points and the installed status are displayed in any column of the Parameter status section, make the setting so that I/O assignments of PLC parameter can match the installed status.
Page 211 7 FUNCTION MELSEC-Q (2) In case of GX Developer Version 6 (SW6D5C-GPPW-E) or later It is possible to confirm the following information for High Performance model QCPUs connected to personal computers with the GX Developer system monitor (see illustration below.) •...
Page 212 7 FUNCTION MELSEC-Q Module’s detailed information This function is used to confirm the detailed information for selected modules. Refer to the instruction manual for details on the relevant intelligent function module and intelligent function modules. Base information Enables the "Overall Information" and "Base Information" to be confirmed. Overall information Enables the number of base units in use and the number of modules mounted on the base units to be confirmed.
Page 213: Led Display
7 FUNCTION MELSEC-Q 7.19 LED Display The High Performance model QCPU has an LED to indicate the High Performance model QCPU operation status on the front of the High Performance model QCPU. The display details of each LED are described below. 7.19.1 LED display (1) The details of the LED display are shown below: LED name...
Page 214 7 FUNCTION MELSEC-Q (2) Method to turn off the LED The LED that is on can be turned off by the following operation. (Except for the reset operation.) Applicable LED Method to Turn LED Off ERR. USER BAT. BOOT Executing the LEDR instruction after resolving the cause of error.
Page 215: Priority Setting
7 FUNCTION MELSEC-Q 7.19.2 Priority setting When multiple factors that can be displayed occur, the display is performed with the following conditions: A stop error is displayed without condition. An operation continue error is displayed according to the priority factor number set as the default.
Page 216 7 FUNCTION MELSEC-Q The description and default priority for the factor number to be set in the special registers SD207 to SD209 are as follows: Factor number Priority Description Remarks (Hexadecimal) AC/DC DOWN Power shutoff UNIT VERIFY ERR. I/O module verification error FUSE BREAK OFF Fuse shutoff SP.UNIT ERROR...
Page 217: High Speed Interrupt Function
7 FUNCTION MELSEC-Q 7.20 High Speed Interrupt Function When an interrupt program is created using the interrupt pointer I49, the QnHCPU can run a program by making high speed, fixed-cycle interrupts at intervals of 0.2ms to 1.0ms. And, the QnHCPU improves the I/O response by refreshing the I/O signals and intelligent function module buffer memories in the parameter-set ranges before and after the execution of the high speed interrupt program.
Page 218 7 FUNCTION MELSEC-Q POINT Since the high speed interrupt function need to pick up interrupts at very short intervals of 0.2ms to 1.0ms with the interrupt pointer I49, please do not run the interrupt programs, which use the other interrupt pointers I0 to I48, I50 to I255, and fixed scan execution type programs.
Page 219: High Speed Interrupt Program Execution
7 FUNCTION MELSEC-Q 7.20.1 High speed interrupt program execution The high speed interrupt program execution function is designed to run an interrupt program according to the setting of high speed interrupt pointer I49. Set the high speed interrupt pointer I49 at "High speed interrupt I49 fixed scan interval" after choosing "PLC system"...
Page 220: High Speed I/O Refresh, High Speed Buffer Transfer
7 FUNCTION MELSEC-Q 7.20.2 High speed I/O refresh, high speed buffer transfer High speed I/O refresh is a function that updates I/O signals between the I/O and intelligent function modules and CPU module at interrupt cycle intervals. High speed buffer transfer is a function that updates data between the intelligent function module buffer memories and CPU module devices at interrupt cycle intervals.
Page 221: Contents
7 FUNCTION MELSEC-Q The settings for high speed I/O refresh and high speed buffer transfer are as follows. Number of Item Sub Item Contents Restrictions Settings Head device No. Up to 6 points for I/O and intelligent function Start (X/Y) (X0 to XFF0/Y0 to YFF0) X input and Y High speed I/O...
Page 222: Processing Time
7 FUNCTION MELSEC-Q 7.20.3 Processing time The following chart shows the processing times of the high speed interrupt function between a start and an end. Main routine program Waiting time High speed interrupt start X input Buffer memory read I49 overhead High speed interrupt program execution Buffer memory write Y output...
Page 223 7 FUNCTION MELSEC-Q Processing Item Processing Time (1) Main base (a) 16 words or less: Time = 0.47 (total number of transferred words) 2.65 (number of settings) 0.95 (b) More than 16 words: Time = 0.55 (total number of transferred words) 0.95 (2) Extension base Buffer memory write...
Page 224: Restrictions
7 FUNCTION MELSEC-Q 7.20.4 Restrictions This section explains the items to be noted when the high speed interrupt function is executed. Depending on the items, a WDT error may occur or high speed interrupt may not be executed at preset cycle intervals if the corresponding restrictions are not satisfied. The restrictions are roughly classified into the following four different items.
Page 225 7 FUNCTION MELSEC-Q Item Restriction When Used Since interrupt is disabled when local devices are changed, high speed interrupt is not available at preset cycle. Local devices Local devices are not available. (The following time is taken. • 390 n for standard RAM •...
Page 226 7 FUNCTION MELSEC-Q (4) Items to be noted in addition to (1) to (3) If "High speed execution" is selected at the "Interrupt program/fixed scan execution program setting" section on the "PLC system" tab screen in thd "(PLC) parameter" dialog box of GX Developer, this setting is invalid for the high speed interrupt function.
Page 227: Module Service Interval Time Reading
7 FUNCTION MELSEC-Q 7.21 Module Service Interval Time Reading The High Performance QCPU can monitor the service interval time (time from service acceptance to next service acceptance) of the intelligent function module, network module or GX Developer. This indicates the frequency at which access to the CPU occurs from outside.
Page 228 7 FUNCTION MELSEC-Q REMARK : The module service interval indicates the time between a transient request such as monitor, test, program read/write. The access interval in cyclic communication from the network module is not stored. 7 - 92 7 - 92...
Page 229: Communication With Intelligent Function Module/Special Function Module
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE (1) Description of intelligent function modules/special function modules High Performance model QCPU allows the use of the Q Series compatible intelligent function modules and the AnS series compatible special function modules.
Page 230: Initial Setting And Automatic Refresh Setting Using Gx Configurator
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.1.1 Initial setting and automatic refresh setting using GX Configurator (1) Initial and automatic refresh settings of intelligent function modules Installing the GX Configurator compatible with the intelligent function module enables the initial setting and automatic refresh setting with GX Developer. When the initial setting and automatic refresh setting of the intelligent function module is designated with GX Developer, you can write/read data without creating the program for the communication with the intelligent function module.
Page 231: Communication Using Device Initial Value
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q (b) Auto refresh setting For the auto refresh setting, designate the device at High Performance model QCPU to store the following data. • Digital output of Q64AD • Maximum/minimum values of Q64AD •...
Page 232: Communication Using From/To Instruction
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.1.3 Communication using FROM/TO instruction (1) FROM/TO instruction At the execution of the FROM/TO instruction, the data stored in the buffer memory of the intelligent function module can be read, or data can be written to the buffer memory of the intelligent function module.
Page 233: Communication Using The Instructions Dedicated For Intelligent Function Modules
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.1.5 Communication using the instructions dedicated for intelligent function modules (1) Description of the instructions dedicated for intelligent function modules The instructions dedicated for intelligent function modules are the instructions that facilitate programming using the functions of the intelligent function modules.
Page 234: Request From Intelligent Function Module To High Performance Model Qcpu
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.2 Request from Intelligent Function Module to High Performance model QCPU 8.2.1 Interrupt from the intelligent function module (1) Interrupt from the intelligent function module High Performance model QCPU executes an interrupt program (I50 to I255) by the interrupt request from the intelligent function module.
Page 235: Communication Between High Performance Model Qcpu And Ans Series Special Function Modules
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.3 Communication Between High Performance model QCPU and AnS Series Special Function Modules The following methods enable the communication between High Performance model QCPU and the special function modules compatible with AnS Series: •...
Page 236: Communication Using From/To Instruction
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.3.2 Communication using FROM/TO instruction (1) FROM/TO instruction At the execution of the FROM/TO instruction, the data stored in the buffer memory of the special function module can be read, or data can be written to the buffer memory of the special function module.
Page 237: Effects Of Quicker Access To The Special Function Module And Countermeasures Against Them
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE MELSEC-Q 8.3.4 Effects of quicker access to the special function module and countermeasures against them (1) Effects of quicker access to the special function module As the scan time of High Performance model QCPU increases, there are some limitations for the execution of the FROM/TO instruction to the AnS-compatible special function module.
Page 238: Parameter List
9 PARAMETER LIST MELSEC-Q 9 PARAMETER LIST There are two types of parameters used in High Performance model QCPU's procedures: "PLC parameters" that are used when operating a PLC and "network parameters" that are used when connecting to the MELSECNET/H or CC-Link system. The following items required for configuring multiple PLC systems onto PLC parameters in function version B High Performance model QCPUs have also been added.
Page 239 9 PARAMETER LIST MELSEC-Q Table 9.1 Parameter List Item Parameter No. Description Designate the label and comment for the CPU module to be used. PLC name — These settings do not affect CPU operation Label 0000 Designates the label setting (name and use). Comment 0001 Designates the comment setting.
Page 240 9 PARAMETER LIST MELSEC-Q Default Value Setting Range Reference Section — — — No setting Max. of 10 characters — No setting Max. of 64 characters — — — — 100 ms 1 to 1000 ms(1 ms units) Section 10.2.10 10.0 ms 0.1 to 100.0 ms Section 10.2.10...
Page 241 9 PARAMETER LIST MELSEC-Q Table 9.1 Parameter List (continued) Item Parameter No. Description PLC RAS — These settings are used for the RAS function. WDT (Watch dog timer) Set the watch dog timer of the CPU module. setting Set the watch dog timer for the use of an initial execution type Initial execution 3000 setting...
Page 242 9 PARAMETER LIST MELSEC-Q Default Value Setting Range Reference Section — — — 200 ms 10 to 2000 ms (10 ms units) Section 4.2.2 No setting 10 to 2000 ms (10 ms units) Section 4.2.1 No setting 10 to 2000 ms (10 ms units) Section 4.2.3 Stop Stop/Continue...
Page 243: Power Supply Module
9 PARAMETER LIST MELSEC-Q Table 9.1 Parameter List (continued) Item Parameter No. Description I/O assignment — Designates the status of installation of each module of the system. Type Designates the type of the installed module. Assign- Designates the model of the installed module. (Memorandum for ment Model name users who do not use the CPU module.)
Page 244 9 PARAMETER LIST MELSEC-Q Default Value Setting Range Reference Section — — — • PLC CPU No.2 to No.4: PLC No.n/Empty (Designate "CPU (empty)" for slots where no CPU module is installed.) • Input/output module and intelligent function module No setting •...
Page 245 9 PARAMETER LIST MELSEC-Q Table 9.1 Parameter List (continued) Item Parameter No. Description Designates parameters for MELSECNET/H, Ethernet and CC- Network parameter Link. MELSECNET/H setting No. of boards in module 5000 Valid module during other 5001 station access Interlink transmission parameter 5002 Routing parameters 5003...
Page 246 9 PARAMETER LIST MELSEC-Q Default Value Setting Range Reference Section — — — No setting • Refer to the Q Corresponding MELSECNET/H manual. — No setting • Refer to the Q Corresponding Ethernet manual. — Refer to the CC-Link manual No setting •...
Page 247 9 PARAMETER LIST MELSEC-Q 1: N and M indicate the following. N: Indicates the module number. M: Indicates the network type. Network Type MELSECNET/10 mode (Control station), MELSECNET/H mode (Control station) MELSECNET/10 mode (Normal station), MELSECNET/H mode (Normal station) MELSECNET/H (Remote master) MELSECNET/H Stand by station 2: N and M indicate the following.
Page 248: Devices
10 DEVICES MELSEC-Q 10 DEVICES This chapter describes all devices that can be used in the High Performance model QCPU. 10.1 Device List The names and data ranges of devices which can be used in the High Performance model QCPU are shown in Table 10.1 below. Table 10.1 Device List Default Values Parameter...
Page 249 10 DEVICES MELSEC-Q Default Values Parameter Reference Class Type Device Name Designated Number of Points Range Used Section Setting Range Intelligent Un\G0 to function Word device Buffer register 65536 points Unchangeable Section 10.5 Un\G65535 module device Index Word device Index register 16 points Z0 to Z15 Unchangeable...
Page 250: Internal User Devices
10 DEVICES MELSEC-Q 10.2 Internal User Devices Internal user devices can be used for various user applications. The "number of usable points" setting is designated in advance (default value) for internal user devices. However, this setting can be changed at the "Device" tab screen in the “(PLC) Parameter"...
Page 251 10 DEVICES MELSEC-Q For timer (T) retentive timer (ST), and Counter (C): For the timer, retentive timer, and counter, 16 points are calculated as 18 words. (T, ST, C total number of points) (Timer, retentive, counter capacity) = 18 (Word) For word devices: For data registers (D) and link registers (W), 16 points are calculated as 16 words.
Page 252: Inputs (X)
10 DEVICES MELSEC-Q 10.2.1 Inputs (X) (1) Definition Inputs transmit commands or data to the High Performance model QCPU from an external device such as push-button switches, selector switches, limit switches, digital switches. Push-button switch Selector switch Input (X) Sequence operation Digital switch If the input point is the Xn virtual relay inside the High Performance model...
Page 253 10 DEVICES MELSEC-Q (2) Reading the inputs There are 2 types of input: "refresh inputs" and "direct access inputs". The refresh input executes an operation with ON/OFF data. The data is read by performing an input refresh before the sequence programs is executed.
Page 254 10 DEVICES MELSEC-Q The same input number can be designated for a refresh input and a direct access input. If the number is used as a refresh input after being used as a direct access input, the operation is executed with the ON/OFF data read by performing a direct access input.
Page 255: Outputs (Y)
10 DEVICES MELSEC-Q 10.2.2 Outputs (Y) (1) Definition Outputs give out the program control results to the external devices such as solenoid, electromagnetic switch, signal lamp and digital display. Signal lamp Digital display Output (Y) Sequence operation Contact Outputs give out the result equivalent to one N/O contact. There are no restrictions on the number of output Yn N/O contacts and N/C contacts used in a program, provided the program capacity is not exceeded.
Page 256 10 DEVICES MELSEC-Q (3) Output method There are 2 types of output: "refresh outputs" and "direct access outputs". The refresh output gives out the ON/OFF data to an output module by performing an output refresh before the sequence program is executed.
Page 257: Internal Relays (M)
10 DEVICES MELSEC-Q 10.2.3 Internal relays (M) (1) Definition Internal relays are auxiliary relays which cannot be latched by the programmable controller's internal latch (memory backup). All internal relays are switched OFF at the following times: • When power is switched from OFF to ON. •...
Page 258: Latch Relays (L)
10 DEVICES MELSEC-Q 10.2.4 Latch relays (L) (1) Definition (a) Latch relays are auxiliary relays which can be latched by the programmable controller's internal latch (memory backup). Latch relay operation results (ON/OFF information) are saved even in the following cases: •...
Page 259: Anunciators (F)
10 DEVICES MELSEC-Q 10.2.5 Anunciators (F) (1) Definition Anunciators are internal relays used for fault detection programs created by the user. (b) When anunciators switch ON, a special relay (SM62) switches ON, and the Nos. and quantity of the anunciators which switched ON are stored at the special registers (SD62 to SD79).
Page 260 10 DEVICES MELSEC-Q (2) Anunciator ON procedure Anunciator ON procedure Anunciator operation can be controlled by the SET F and OUT F instructions. The SET F instruction switches the anunciator ON only at the leading edge (OFF to ON) of the input condition, and keeps the anunciator ON when the input condition switches OFF.
Page 261 10 DEVICES MELSEC-Q The OUT F instruction can execute ON/OFF of the anunciator No. by the same instruction. However, if an anunciator is switched OFF by the OUT F instruction, the "processing at anunciator OFF" (item (b) below) is not performed. Execute the RST F , LEDR or BKRST instructions after the anunciator has been switched OFF by the OUT F instruction.
Page 262 10 DEVICES MELSEC-Q Special register (SD62 to SD79) data operation when an anunciator is switched OFF by the RST F instruction The anunciator No. which was switched OFF is deleted, and all subsequent anunciator Nos. are moved up to fill the empty space. If the anunciator No.
Page 263: Edge Relay (V)
10 DEVICES MELSEC-Q 10.2.6 Edge relay (V) (1) Definition An edge relay is a device which stores the operation results (ON/OFF information) from the beginning of the ladder block. Edge relays can only be used at contacts, and cannot be used as coils. Edge relay Stores the X0, X1 and X10 operation results The same edge relay number cannot be used twice in programs executed...
Page 264: Link Relays (B)
10 DEVICES MELSEC-Q 10.2.7 Link relays (B) (1) Definition A link relay is the High Performance model QCPU relay used to refresh the High Performance model QCPU from the MELSECNET/H network module's link relay (LB) and to refresh the MELSECNET/H network module's link relay (LB) from the High Performance model QCPU data.
Page 265: Link Special Relays (Sb)
10 DEVICES MELSEC-Q 10.2.8 Link special relays (SB) (1) Definition A link special relay indicates the communication status and error detection of an intelligent function module, such as the MELSECNET/H Network Module. Because link special relays are switched ON and OFF in accordance with various problems which may occur during a data link, they serve as a tool for identifying data link problems.
Page 266: Timers (T)
10 DEVICES MELSEC-Q 10.2.10 Timers (T) Timers are of up-timing, with the time measurement beginning when the coil switches ON, and ending (time out) when the current value exceeds the set value. The current value matches the set value when a "time-out" occurs. There are two types of timers: a low/high speed that allows the current value to return to "0"...
Page 267 10 DEVICES MELSEC-Q High-speed timers (1) Definition High speed timers are valid only while the coil is ON. A high speed timer is marked with a symbol "H". The time measurement begins when the timer's coil switches ON, and the contact switches ON when the time elapses.
Page 268 10 DEVICES MELSEC-Q Retentive timers (1) Definition Retentive timers measure the "coil ON" time. The measurement begins when the timer coil switches ON, and the contact switches ON when a time-out (coil OFF) occurs. Even when the timer coil is OFF, the current value and the contact ON/OFF status are saved.
Page 269 10 DEVICES MELSEC-Q Timer Processing and accuracy (a) When an OUT T instruction is executed, the following is processed: timer coil ON/OFF, current value update and contact ON/OFF processing. Timer current value update and contact ON/OFF processing are not performed at END processing.
Page 270 10 DEVICES MELSEC-Q The timer response accuracy from when reading input (X), until when outputing it is + (2-scan time + timer time limit setting). Precautions for using timers The following are a few precautions regarding timer use: A given timer cannot be designated (by OUT T ) more than once in a single scan.
Page 271: Counters (C)
10 DEVICES MELSEC-Q 10.2.11 Counters (C) Counters are "up-timing" types, with the contact being switched ON when the count value equals the set value (count-out condition). There are two counter types: counters which count the number of input condition start- ups (leading edges) in sequence programs, and counters which count the number of interrupt factor occurrences.
Page 272 10 DEVICES MELSEC-Q Multiple counters can be used within a single scan to achieve the maximum counting speed. In such cases, the direct access input (DX ) method should be used for the counter input signals. Sequence program OUT C execution intervals (3) Resetting the counter Counter current values are not cleared even if the OUT C...
Page 273 10 DEVICES MELSEC-Q Interrupt counters (1) Definition Interrupt counters are devices which count the number of interrupt factor occurrences. (2) Count processing The interrupt counter's current value is updated when an interruption occurs. It is not necessary to create a program which includes an interrupt counter function.
Page 274 10 DEVICES MELSEC-Q (4) Precautions One interrupt pointer is insufficient to execute interrupt counter and interrupt program operation. Moreover, an interrupt program cannot be executed by an interrupt counter setting designated at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.
Page 275: Data Registers (D)
10 DEVICES MELSEC-Q 10.2.12 Data registers (D) (1) Definition Data registers are memory devices which store numeric data (-32768 to 32767, or 0000 to FFFF Data registers, which consist of 16 bits per point, read and write data in 16- bit units.
Page 276: Link Registers (W)
10 DEVICES MELSEC-Q 10.2.13 Link registers (W) (1) Definition A link register is the High Performance model QCPU memory used to refresh the High Performance model QCPU with data from the link registers (LW) of intelligent function modules including MELSECNET/H network module.
Page 277: Link Special Registers (Sw)
10 DEVICES MELSEC-Q (2) Using link registers in a network system In order to use link registers in the network system, network parameter settings must be made. Link registers not set in the network parameter settings can be used as data registers.
Page 278: Internal System Devices
10 DEVICES MELSEC-Q 10.3 Internal System Devices Internal system devices are used for system operations. The allocations and sizes of internal system devices are fixed, and cannot be changed by the user. 10.3.1 Function devices (FX, FY, FD) (1) Definition Function devices are used in sub-routine programs with arguments to permit data transfers between the sub-routine program with argument, and the CALL source for that sub-routine.
Page 279 10 DEVICES MELSEC-Q Function registers (FD) • Function registers are used to designate data transfers between the sub- routine CALL source and the sub-routine program. • The function register I/O condition is automatically determined by the High Performance model QCPU. If the sub-routine program data is the source data, the data is designated as sub-routine input data.
Page 280: Special Relays (Sm)
10 DEVICES MELSEC-Q 10.3.2 Special relays (SM) (1) Definition A special relay is used to store High Performance model QCPU status data. (2) Special relay classifications Special relays are classified according to their applications, as shown below. (a) For fault diagnosis : SM0 to SM199 (b) System information : SM200 to SM399...
Page 281: Special Registers (Sd)
10 DEVICES MELSEC-Q 10.3.3 Special registers (SD) (1) Definition A special register is used to store High Performance model QCPU status data (diagnosis and system information). (2) Special register classifications Special registers are classified according to their applications, as shown below. For fault diagnosis : SD0 to SD199 System information...
Page 282: Link Direct Devices (J \ )
10 DEVICES MELSEC-Q 10.4 Link Direct Devices (J \ ) (1) Definition At END processing of sequence program, a data refresh (data transfer) is performed between the High Performance model QCPU and the MELSECNET/H network modules. Link direct devices are used to directly access the link devices in the MELSECNET/H network modules.
Page 283 10 DEVICES MELSEC-Q Although writing is also allowed in the "refresh range" portion of the link device range (specified by refresh parameters), the link module's link device data will be rewritten when a refresh operation occurs. Therefore, when writing by link direct device, the same data should also be written to the High Performance model QCPU related devices designated by refresh parameter.
Page 284 10 DEVICES MELSEC-Q (3) Differences between "link direct devices" and "link refresh" The differences between "link direct devices" and "link refresh" are shown in Table 10.4 below. Table 10.4 Differences Between "Link Direct Devices" and "Link Refresh" Item Link Direct Device Link Refresh Link relay J \K4B0 or later...
Page 285: Intelligent Function Module Devices (U \G )
10 DEVICES MELSEC-Q 10.5 Intelligent Function Module Devices (U \G ) (1) Definition The intelligent function module devices allow the High Performance model QCPU to directly access the buffer memories of intelligent function modules/special function modules which are mounted on at the main base unit and extension base units.
Page 286: Index Registers (Z)
10 DEVICES MELSEC-Q 10.6 Index Registers (Z) (1) Definition Index registers are used in the sequence program for indirect setting (index qualification) designations. An index register point is used for index modification. MOVP K5 Z0 SM400 D0Z0 K4Y30 Index registers consist of 16 bits per point. There are 16 index registers (Z0-Z15).
Page 287: Switching Between Scan Execution Type Programs And Low Speed Execution Type Programs
10 DEVICES MELSEC-Q 10.6.1 Switching between scan execution type programs and low speed execution type programs When switching from a scan execution type programs or low speed execution type program to another program type, the index register (Z0 to Z15) data is saved (protected) and reset.
Page 288: Switching Between Scan/Low Speed Execution Type Programs And Interrupt/ Fixed Scan Execution Type Programs
10 DEVICES MELSEC-Q 10.6.2 Switching between scan/low speed execution type programs and interrupt/fixed scan execution type programs The "PLC system" tab screen in the “(PLC) Parameter" dialog box provides the option to save (protect) or restore index register data (Z0 to Z15) when switching between a scan execution type program and a low speed execution type program or between an interrupt program and a fixed scan execution type program.
Page 289 10 DEVICES MELSEC-Q (2) When the "High speed execution" check box is checked: If a scan execution type program/low speed execution type program is switched to an interrupt program/fixed scan execution type program, index register data will not be saved/restored. If data is written to index registers by using an interrupt program/fixed scan execution type program, the values of index registers used for an scan/low speed execution type program will be corrupted.
Page 290: File Registers (R)
10 DEVICES MELSEC-Q 10.7 File Registers (R) (1) Definition File registers are expansion devices for data registers. File register data is stored in files in the standard RAM, the memory card. Refer to the table as follows: CPU Module Type Number of File Registers Q02CPU 32k points...
Page 291: File Register Capacity
10 DEVICES MELSEC-Q 10.7.1 File register capacity (1) Using the Standard RAM A maximum of 32 k file register points can be stored in the standard RAM. The standard RAM holds file registers and local devices. When local devices are not used, all 32 k points can be assigned for file registers.
Page 292: Registering The File Registers
10 DEVICES MELSEC-Q 10.7.3 Registering the file registers To use file registers, register the file registers with the High Performance model QCPU in the following steps. Start Setting of file register to be used ...."PLC file" tab screen at (PLC) "parameter" dialog box "Use the following files"...
Page 293 10 DEVICES MELSEC-Q (1) Designating file registers for use The standard RAM or the memory card file registers which are to be used in the sequence program are determined at the "PLC file" tab screen in the “(PLC) Parameter" dialog box. (a) When selecting "Not used"...
Page 294 10 DEVICES MELSEC-Q POINT File registers dedicated to each program may not be designated with some instructions. Refer to the allowable device in the programming manual of each instruction for details. (c) When selecting "Use the following file" This setting should be selected when a given file register is to be shared by all executed programs.
Page 295 10 DEVICES MELSEC-Q (3) Registering the File Register File with the High Performance model QCPU If you click on the following check boxes at the "PLC file" tab screen in the “(PLC) Parameter" dialog box, you must register a file register file with the High Performance model QCPU: •...
Page 296: File Register Designation Method
10 DEVICES MELSEC-Q 10.7.4 File register designation method (1) Block switching format The block switching format designates the number of file register points in 32k point (R0 to R32767) units. If multiple blocks are used, switch to the block No. to be used in the RSET instruction for further file register settings.
Page 297: Precautions In Using File Registers
10 DEVICES MELSEC-Q 10.7.5 Precautions in using file registers (1) Using file register Nos. not registered or outside the registered range (a) When file register files are not registered in the High Performance model QCPU, no error occurs even if reading/writing to file registers Reading data from a file register results in the following: •...
Page 298 10 DEVICES MELSEC-Q Checking the file register capacity Check The file register capacity used for each sequence program. Determine if the file register capacity exceeds the number of points used, on the basis of the total file register capacity set in SD647 in the sequence program.
Page 299: Nesting (N)
10 DEVICES MELSEC-Q 10.8 Nesting (N) (1) Definition Nesting devices are used to nest MC or MCR master control instructions when programming operating conditions. (2) Designation method with master control The master control instructions are used to open and close the ladders' common bus so that switching of ladders may be executed efficiently by the sequence program.
Page 300: Pointers (P)
10 DEVICES MELSEC-Q 10.9 Pointers (P) (1) Definition Pointer devices are used in jump instructions (CJ, SCJ, JUMP) or sub-routine call instructions (CALL, ECALL). A total of 4096 pointers can be used (total for all programs being executed). (2) Pointer applications Pointers are used in jump instructions (CJ, SCJ, JMP) to designate jump destinations and labels (jump destination beginning).
Page 301: Common Pointers
10 DEVICES MELSEC-Q (2) Number of local pointer points Local pointers can be divided among all the programs stored in the program memory. The local pointer No. ranges from P0 to the highest No. of the local pointer in use. (The High Performance model QCPU's OS computes the number of points used.) Even if only P99 is used in a program, for example, the number of points used will be counted as 100 between P0 and P99.
Page 302 10 DEVICES MELSEC-Q (2) Common pointer range of use In order to use common pointers, the first common pointer No. must be designated at the "PLC system" tab screen in the “(PLC) Parameter" dialog box. A range of common pointers starts from a specified pointer number to P4095. However, only pointer numbers subsequent to the local pointer range can be designated by parameter setting as common pointers.
Page 303: Interrupt Pointers (I)
10 DEVICES MELSEC-Q 10.10 Interrupt Pointers (I) (1) Definition Interrupt pointers are used as labels at the beginning of interrupt programs. Interrupt pointer (interrupt program label) Interrupt program IRET A total of 256 interrupt points (I0 to I255) can be used (total for all programs being executed).
Page 304 10 DEVICES MELSEC-Q A list of interrupt pointer Nos. and interrupt factors is given in Table 10.5 below. Table 10.5 List of Interrupt Pointer Nos. and Interrupt Factors Priority Priority I No. Interrupt Factors I No. Interrupt factors Ranking Ranking 1st point Errors that stop operation 2nd point...
Page 305: Other Devices
10 DEVICES MELSEC-Q 10.11 Other Devices 10.11.1 SFC block device (BL) This device is used for checking if the block designated by the SFC program is valid. For details on the use of SFC block devices, refer to the QCPU(Q mode)/QnACPU Programming Manual (SFC).
Page 306: I/O No. Designation Device (U)
10 DEVICES MELSEC-Q 10.11.4 I/O No. designation device (U) (1) Definition I/O No. designation devices are used with instructions dedicated to intelligent function module to designate I/O numbers. (2) Designating the I/O No. designation device I/O No. designation devices are designated with the intelligent function module instructions as shown below.
Page 307: Macro Instruction Argument Device (Vd)
10 DEVICES MELSEC-Q 10.11.5 Macro instruction argument device (VD) (1) Definition Macro instruction argument devices are used with ladders registered as macros. When a VD setting is designated for a ladder registered as a macro, conversion to the designated device is performed when the macro instruction is executed.
Page 308: Constants
10 DEVICES MELSEC-Q 10.12 Constants 10.12.1 Decimal constants (K) (1) Definition Decimal constants are devices which designate decimal data in sequence programs. They are designated as "K "settings (e.g. K1234), and are stored in the High Performance model QCPU in binary (BIN) code. See Section 4.8.1 for details on binary code.
Page 309: Real Numbers (E)
10 DEVICES MELSEC-Q 10.12.3 Real numbers (E) (1) Definition Real numbers are devices which designate real numbers in the sequence program. Real numbers are designated as "E "settings (e.g. E1.234). EMOVP E1.234 D0 See Section 4.8.4 for details on real numbers. (2) Designation range -126 -126...
Page 310: Convenient Uses For Devices
10 DEVICES MELSEC-Q 10.13 Convenient Uses for Devices When executing multiple programs in the High Performance model QCPU, local devices among the internal user devices can be designated to execute each of the programs in an independent manner. Moreover, the device initial settings allow the data setting for devices and intelligent function modules/special function modules without using a program.
Page 311 10 DEVICES MELSEC-Q (2) Local devices Local devices are used independently by the programs. The use of local devices permits programming of multiple "independent execution" programs without regard to other programs. Local devices data can be stored in the standard RAM and the memory card.
Page 312 10 DEVICES MELSEC-Q (d) Local device designation In order to use the above devices as local devices, the usable local device range must be designated at the "Device" tab screen in the “(PLC) Parameter" dialog box. Note that the range designated for local devices applies to all programs, and cannot be changed for individual programs.
Page 313 10 DEVICES MELSEC-Q Switching over local devices by setting ON/OFF for a special relay (SM776) SM776 Executes calculation by the local devices that are used by the file where the sub-routine program was called Executes calculation by the local devices that are used by the file where the sub-routine program is stored.
Page 314 10 DEVICES MELSEC-Q Using local devices when executing an interrupt/fixed scan execution type program It is possible to use local devices in the file where an interrupt/fixed scan execution type program is stored when executing an interrupt/fixed scan execution type program. The local devices can be set available/unavailable by special relay "SM777"...
Page 315 10 DEVICES MELSEC-Q Cautions • If SM777 is ON, the local device data is read before the interrupt/fixed scan execution type program is executed and the local device data is saved after the execution of the IRET instruction. Accordingly, scan time increases when an interrupt/fixed scan execution type program is executed once with the setting of "SM777: ON".
Page 316: Device Initial Values
10 DEVICES MELSEC-Q 10.13.2 Device initial values (1) Definition Using device initial value registers, the data used for a program in device or intelligent function module buffer memories without using a data setting program. The use of device initial values provides a shortcut to specify device data in a program without using a device data setting program (initial program).
Page 317 10 DEVICES MELSEC-Q Device initial values can be used by the following devices: 1) Timer present value (T) 7) Link special register (SW) 2) Retentive timer present value (ST) 8) File register (R0 to R32767) 3) Counter present value (C) 9) Intelligent function module device 4) Data register (D) (U \G )
Page 318 10 DEVICES MELSEC-Q (3) Precautions for the use of device initial values In cases where both device initial value data and latch range data are overlapped, the device initial value data takes priority. Therefore, the latch range data is rewritten by device initial value data at power ON.
Page 319: High Performance Model Qcpu Processing Time
11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME MELSEC-Q 11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME This chapter describes how to estimate the length of High Performance model QCPU processing time. 11.1 Reading High Performance model QCPU's Scan Time The length of scan time is the total of the following times: •...
Page 320: Factors Responsible For Extended Scan Time
11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME MELSEC-Q 11.2 Factors Responsible for Extended Scan Time The following functions increase the length of scan time. When using any of the following functions, add a value of extended time to values obtained from Section 11.1. •...
Page 321 11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME MELSEC-Q (4) GX Developer Monitoring GX Developer monitoring requires additional processing time. Add the GX Developer monitoring time to the total processing time. The table below shows the processing time required when 64 data register points are assigned by the registered monitor.
Page 322: Factors Responsible For Shortened Scan Time
11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME MELSEC-Q (8) File register File register requires additional processing time. Add the processing time of file registers to the total processing time. CPU Type Processing Time Q02CPU 1.03 ms Standard RAM Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.41 ms Q02CPU 0.94+0.2 n ms...
Page 323: Procedure For Writing Programs To High Performance Model Qcpu 12- 1 To-12
12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU This chapter describes the procedure for writing programs created at the GX Developer to the High Performance model QCPU. 12.1 Writing Procedure for 1 Program This section describes the procedure for writing one program to the High Performance model QCPU and executing it.
Page 324: Procedure For Writing Programs To The High Performance Model Qcpu
12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q 12.1.2 Procedure for writing programs to the High Performance model QCPU The procedure for writing programs and parameters created with GX Developer to the High Performance model QCPU standard ROM is shown below. In order to write programs and parameters to the High Performance model QCPU standard ROM, the valid parameters settings must be designated by the High Performance model QCPU DIP switches (SW2, SW3), and the boot settings must be...
Page 325 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q Use the device See Section 10.13.2. initial value? Right-click on the device memory and select "Add" to specify device initial value data. Right-click on a device initial value and select "Add" to spe- cify a device initial value range.
Page 326 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q In Write to PLC(Flash ROM) in the GX Developer online mode, select "Standard ROM" and write the parameter data and crated program. Use the CPU module's RESET/ L.CLR switch to execute a reset. CPU module's "BOOT"...
Page 327: Procedure For Multiple Programs
12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q 12.2 Procedure for Multiple Programs This section describes the procedure for writing multiple programs split up according to function, process, designer to the High Performance model QCPU and executing them.
Page 328: Procedure For Writing Programs To The High Performance Model Qcpu
12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q 12.2.2 Procedure for writing programs to the High Performance model QCPU The procedure for writing programs and parameters created by GX Developer to the memory card mounted in the High Performance model QCPU memory card interface is shown below.
Page 329 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q Use the device See Section 10.13.2. initial value? Right-click on the device memory and select "Add" to specify device initial value data. Right-click on a device initial value and select "Add" to specify a device initial value range.
Page 330 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU MELSEC-Q In the boot file setting item in the PLC parameter, designate the file name of parameter and program to be read from the memory card. In the program settings in the PLC parameter, designate the name of the program to be exe- cuted, and its execution condition.
Page 331: Outline Of Multiple Plc Systems
13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q 13 OUTLINE OF MULTIPLE PLC SYSTEMS 13.1 Features (1) Multi control Since each system is not configured on one High Performance model QCPU but on the High Performance QCPU, Motion CPU, and PC CPU module according to the system, the development efficiency and ease of maintenance of the system can be enhanced.
Page 332 13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q (4) Communication can be made between CPU modules in the multiple PLC system The following data transfer can be made between CPU modules in the multiple PLC system. Automatic refresh setting at GX Developer enables the data transfer between CPU modules.
Page 333: Outline Of Multiple Plc Systems
13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q 13.2 Outline of Multiple PLC Systems (1) What is a multiple PLC system? A multiple PLC system is a system in which main base units are mounted on several (maximum four) High Performance model QCPUs and motion CPU in order to control the I/O modules and intelligent function modules.
Page 334 13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q (2) Multiple PLC system setup It is necessary to set up the "Number of mounted CPU modules" and the "Control PLC" with PLC parameters in all CPU modules onto which main base units are mounted in order to control a multiple PLC system (see Chapter 9.) (3) Multiple PLC system access range It is possible for a multiple PLC system's control PLC to perform the I/O...
Page 335: Differences With Single Cpu Systems
13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q 13.3 Differences with Single CPU Systems The differences between single CPU systems and multiple PLC systems are explained below. (1) Function versions (see Sections 14.2.1 to 14.2.5) Function version B High Performance model QCPUs are supported by multiple PLC systems.
Page 336 13 OUTLINE OF MULTIPLE PLC SYSTEMS MELSEC-Q (6) Interactive transmission with non-control PLCs (see Chapter 17) It is possible to control I/O modules and intelligent function modules controlled by the host PLC in the same way as on an single CPU system. It is not possible to output ON.OFF data to modules that are not controlled by the host PLC or write in the buffer memory of intelligent function modules.
Page 337: System Configuration Of Multiple Plc Systems
PLC system configuration. 14.1 System Configuration This section explains the equipment configuration of multiple PLC systems, the connections with peripheral device, and an output of the system's configuration. (1) Equipment configuration of multiple PLC system MITSUBISHI MITSUBISHI LITHIUM BATTERY QCPU(Q02CPU,Q02HCPU, Memory card...
Page 338 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q (2) Configuration of peripheral device MITSUBISHI Memory card High performance model QCPU USB cable (Q2MEM-1MBS,Q2MEM-2MBS, (To be procured yourself) (Q02CPU,Q02HCPU,Q06HCPU, Q2MEM-2MBF,Q2MEM-4MBF, Used only for Q02HCPU,Q06HCPU Q12HCPU,Q25HCPU) Q2MEM-8MBA,Q2MEM-16MBA, ,Q12HCPU and Q25HCPU Q2MEM-32MBA) RS-232 cable...
Page 339 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q Main base unit (Q312B) Slot No. 0 1 2 3 4 5 6 7 8 9 10 11 Extension cable The figure shows the configuration Extension base unit (Q612B) when 32-I/O modules are mounted 1 extension 13 14 15 16 17 18 19 20 21 22 23 stages...
Page 340: Precautions For Multiple Plc System Configuration
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2 Precautions For Multiple PLC System Configuration 14.2.1 Function versions of High Performance model QCPU, motion CPUs and PC CPU module that can be used, and their mounting positions (1) Function versions (a) Allowable function versions and version confirmation method To configure a multiple PLC system, use the High Performance model QCPU and Motion CPU of function version B.
Page 341 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q (2) High Performance model QCPU, motion CPU and PC CPU module mounting positions Up to four modules of High Performance model QCPU can be mounted in the CPU slots (starting from the slot on the right side of power supply module closely) and the neighboring slots up to slot 2.
Page 342 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q Number of CPUs Mounting positions of CPU modules 1: The PC CPU module occupies two slots. Motion CPUs are mounted together on the slot to the right of the High Performance model QCPU. High Performance model QCPUs cannot be mounted to the right of Motion CPUs.
Page 343 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q POINT To add a High Performance model QCPU or Motion CPU to a system where the PC CPU module is used, shift the PC CPU module to the right because no CPU module is allowed on the right side of the PC CPU module.
Page 344 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.2 Precautions when using Q Series I/O modules and intelligent function modules (1) Compatible I/O modules All I/O modules (QX , QY ) are compatible with to multiple PLC system. They can be used by setting any of PLC No.1 to No.4 as a control PLC. (2) Compatible intelligent function modules The intelligent function modules compatible with the multiple PLC system are those of function version B or later.
Page 345: Limitations When Mounting Ans Series Corresponding I/O Modules And Special Function Modules
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.3 Limitations when mounting AnS Series corresponding I/O modules and special function modules (1) Compatible I/O modules and special function modules AnS Series corresponding I/O modules and special function modules (compact types) can be used with the High Performance model QCPU. (2) Control PLCs The AnS Series corresponding I/O modules or special function module can be controlled by only one PLC (control PLC) of the PLCs No.1 to No.4 when...
Page 346 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q (3) Ranges of access to control and non-control modules The following table indicates accessibility to the control and non-control modules in the multiple PLC system. Accessibility Access target Non-control module (I/O setting outside of the group) Control module Disabled Enabled...
Page 347: Modules That Have Mounting Restrictions
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.4 Modules that have mounting restrictions The following table indicates restrictions on the number of modules that can be mounted in multiple PLC systems. Ensure that the number of modules mounted is within these ranges.
Page 348: Compatible Gx Developers And Gx Configurators
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.5 Compatible GX Developers and GX Configurators (1) Compatible GX Developers GX Developer Version 6 (SW6D5C-GPPW-E) or later are compatible with on multiple PLC systems. GX Developer Version 5 (SW5D5C-GPPW-E) or earlier are not compatible with multiple PLC system.
Page 349: Parameters That Enable The Use Of Multiple Plc Systems
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.6 Parameters that enable the use of multiple PLC system (1) Parameters that enable the use of multiple PLC system Compared with the single CPU system, the multiple PLC system includes the "No.
Page 350 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q After parameters such as multiple PLC settings are changed, reflect the changes to keep uniformity among all PLCs in the multiple PLC system, then reset the PLC No.1. It is possible to transfer across and use the CPU settings and I/O Assignments set up for other projects with GX Developer.
Page 351 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q Operation mode setting (optional) This is set to continue operation of other PLCs where a stopping error has not occurred when an error occurs at any of PLCs No.2 to No.4. The operation mode for the PLC No.1 cannot be changed (all PLCs will suspend operations when a stop error is triggered for the PLC No.1.) See Section 14.2.8 for further details.
Page 352 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q (3) Multiple PLC setting and I/O Assignment checks Checks, as shown in table 14.4, will be run to ascertain that all CPU modules have the same settings (sameness check) when the description column in table 14.3 has been set with the "O"...
Page 353: Resetting The Multiple Plc System
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.7 Resetting the multiple PLC system It is possible to reset the entire multiple PLC system by resetting the PLC No.1. The CPU modules for PLC No.2 to No.4, I/O modules and intelligent function modules will be reset when the PLC No.1 is reset.
Page 354: Processing When High Performance Model Qcpu Stop Errors Occur
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.8 Processing when High Performance model QCPU stop errors occur The operations for the entire system will differ when a PLC No.1 stop error occurs and when any of PLC No.2 to No.4 stop error occurs in the multiple PLC system. (1) When a stop error occurs at the PLC No.1 A "MULTIPLE PLC DOWN (error code: 7000)"...
Page 355 14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q POINT A "MULTIPLE PLC DOWN" stop error will be occur for the PLC on which the error was detected when a stop error occurs. There are cases where the timing of error detection will search for the PLC on which the stop error that has caused the "MULTIPLE PLC DOWN"...
Page 356: Reducing The Time Required For Multiple Plc System Processing
14 SYSTEM CONFIGURATION OF MULTIPLE PLC SYSTEM MELSEC-Q 14.2.9 Reducing the time required for multiple PLC system processing (1) Multiple PLC system processing A bus (base unit pattern, extension cable) is used by the CPU module when accessing the I/O module and intelligent function module, and this bus cannot be used by plural CPU module at the same time.
Page 357: Allocating Multiple Plc System I/O Numbers
15 ALLOCATING MULTIPLE PLC SYSTEM I/O NUMBERS MELSEC-Q 15 ALLOCATING MULTIPLE PLC SYSTEM I/O NUMBERS 15.1 Concept behind Allocating I/O Numbers Multiple PLC systems possess I/O numbers to enable interactive transmission between the CPU modules and the I/O modules and intelligent function modules, and I/O numbers to enable interactive transmission between the CPU modules.
Page 358: I/O Number Of High Performance Model Qcpu, Motion Cpu And Pc Cpu Module
15 ALLOCATING MULTIPLE PLC SYSTEM I/O NUMBERS MELSEC-Q 15.1.2 I/O number of High Performance model QCPU, Motion CPU and PC CPU module I/O numbers are allocated to the CPU modules with the multiple PLC system in order to allow interactive communications between the CPU modules with the following commands.
Page 359 15 ALLOCATING MULTIPLE PLC SYSTEM I/O NUMBERS MELSEC-Q 15.2 Purpose of PC Parameter I/O Allocations with GX Developer I/O allocations are performed with GX Developer in the following cases. (1) Setting up control PLCs Sets up the High Performance model QCPU/motion CPU/PC CPU module that are to control the multiple PLC system's I/O modules and intelligent function modules.
Page 360: Communication Between Cpu Modules In Multiple Plc System
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM It is possible to perform the following interactive transmission between each CPU modules with a multiple PLC system. • Automatically refreshing the device data between each CPU modules with multiple PLC system parameter settings.
Page 361: Automatic Refresh Of Cpu Shared Memory
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16.1 Automatic Refresh of CPU Shared Memory (1) Automatic refresh of CPU shared memory Automatic refresh of the CPU shared memory is a function of automatic data transfer between CPU PLCs in END processing of the CPU. As the device memory data of other PLCs is automatically read when the automatic refresh function is used, is possible for the host PLC to use the device data of other PLCs.
Page 362 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q (2) Automatic refresh settings Set the points to be transmitted by each CPU and the device in which the data is to be stored with the PLC parameter multiple PLC settings for when automatic refresh is to performed.
Page 363 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 4): The CPU shared memory occupied with automatic refresh refreshing becomes the total of setting 1 to setting 4. The first and last addresses of the CPU shared memory being used will be displayed in hexadecimals when the number of transmission points are set.
Page 364 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q The CPU devices are set as follows. • It is possible to change the device and set up settings 1 to 4. The same devices can also be specified as long as the device range for settings 1 to 4 are not duplicated.
Page 365 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q • Each of the setting 1 to setting 4 devices can be set up independently. For example, the PLC No.1 can be set up as a link relay, and the PLC No.2 can be set up as an internal relay.
Page 366 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q An outline of the operations when the automatic refresh function is divided into four ranges (Setting 1: Link relay (B), Setting 2: Link register (W), Setting 3: Data register (D), Setting 4: Internal relay (M)) and then performed is shown in the illustration below.
Page 367 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q There are cases where old data and new data will become mixed up for each PLC depending on the timing of refreshing the host PLC and reading data from other PLCs. When performing the automatic refresh function, create an interlock program similar to the one shown below that uses the first device to be refreshed for each PLC, and do not use the data from other PLCs when old...
Page 368: Communication With Multiple Plc Instructions And Intelligent Function Module Devices
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16.2 Communication with Multiple PLC Instructions and Intelligent Function Module Devices (1) Communication with multiple PLC instructions (S. TO instruction / FROM instruction) and intelligent function module device (U \G ) The High Performance model QCPU of a multiple PLC system can use an S.
Page 369 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q (2) Precautions The following values are set in the CPU module's first I/O number with the FROM instruction, the S. TO instruction and instructions that use U \G . PLC No. PLC No.1 PLC No.2 PLC No.3...
Page 370: Interactive Communications Between The High Performance Model Qcpu And Motion Cpu
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16.3 Interactive Communications between The High Performance model QCPU and Motion 16.3.1 Control commands from the High Performance model QCPU to the Motion CPU It is possible to issue control commands from the High Performance model QCPU to the Motion CPU, and read and write device data with the Motion dedicated PLC instructions listed below.
Page 371: Reading And Writing Device Data
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16.3.2 Reading and writing device data It is possible to read and write device data into the Motion CPU/PC CPU module from the High Performance model QCPU with the the communication dedicated instructions between multiple PLCs listed in the table below.
Page 372: Cpu Shared Memory
16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q 16.4 CPU Shared Memory The CPU shared memory is for exchanging data between CPU modules, and consists of 4,096 words between 0H and FFF The CPU shared memory consists of four areas; the host PLC operation information area, the system area, the automatic refresh area, and the user's free area.
Page 373 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q (1) Host PLC operation information area (0 to 1FF The following information is stored in the host PLC with multiple PLC systems. These will all remain as 0 and will not change in the case of single CPU systems.
Page 374 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE PLC SYSTEM MELSEC-Q System area (200 to 7FF The area used by the High Performance model QCPU, Motion CPU and PC CPU module systems (OS.) This is used by the OS when communication dedicated instructions between multiple PLCs are executed.
Page 375: Communications Between The Multiple Plc System's I/Omodules And Intelligent Function Modules
17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES MELSEC-Q 17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES 17.1 Range of Control PLC Communications The relationship between control PLCs and control modules (I/O modules, intelligent function modules, special function modules) is the same as with independent CPU systems.
Page 376 17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES MELSEC-Q (1) Loading input (X) from input modules and intelligent function modules The "Out of group input/output settings" setting in the PLC parameter's multiple PLC settings determines whether input can be loaded from input modules and intelligent function modules being controlled by other PLCs.
Page 377 17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES MELSEC-Q (2) Loading output (Y) The "Out of group input/output settings" setting in the PLC parameter's multiple PLC settings determines whether output can be loaded from output modules and intelligent function modules being controlled by other PLCs.
Page 378 17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES MELSEC-Q (3) Output to output modules and intelligent function modules It is not possible to output ON/OFF data to non-control modules. ON/OFF will be performed within the High Performance model QCPU when the output from output modules and intelligent function modules controlled by other PLCs, such as sequence programs, have been set to ON/OFF, but this will not be output to output modules or intelligent function modules.
Page 379 17 COMMUNICATIONS BETWEEN THE MULTIPLE PLC SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES MELSEC-Q (5) Accessing MELSECNET/H modules Only control PLCs can access MELSECNET/H modules. Link direct devices cannot be used in MELSECNET/H modules being controlled by other PLCs. "OPERATION ERROR (error code: 4102)" occurs if a program that uses link direct devices is used in MELSECNET/H modules being controlled by other PLCs.
Page 380: Processing Time For Multiple Plc System High Performance Model Qcpus
18 PROCESSING TIME FOR MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL QCPUs MELSEC-Q 18 PROCESSING TIME FOR MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL QCPUs 18.1 Concept behind CPU Scanning Time The concept behind multiple PLC system scanning time is the same as the single CPU system.
Page 381: Factor To Prolong The Scan Time
18 PROCESSING TIME FOR MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL QCPUS MELSEC-Q 18.2 Factor to Prolong the Scan Time The processing time for multiple PLC systems is prolonged in comparison with single CPU systems when the following functions are used. Add the following values to the values calculated in Sections 11.1 and 18.a to acquire the amount of time used by these functions.
Page 382 18 PROCESSING TIME FOR MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL QCPUS QCPUS MELSEC-Q (2) MELSECNET/H refresh The amount of time required for performing the refresh process between High Performance model QCPU and MELSECNET/H network modules. Refer to the following manual for details on the refresh time for MELSECNET/H.
Page 383: Starting Up The Multiple Plc System
19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q 19 STARTING UP THE MULTIPLE PLC SYSTEM This Chapter explains the standard procedures for starting up the multiple PLC system. 19.1 Flow-chart for Starting Up the Multiple PLC System Start Clarification of function sharing in multiple ••••••••••••••••••••...
Page 384 19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q Select RUN at the RUN/STOP switch of the QCPU for PLC RUN/STOP switch setting of all PLCs •••••••••••••••••••• No.1 to No.4. Cancellation of resetting of QCPU of Set the RESET/L. CLR switch of the QCPU for the PLC No.1 ••••••••••••••••••••...
Page 385: Setting Up The Multiple Plc System Parameters (Multiple Plc Settings, Control Plc Settings)
19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q 19.2 Setting Up the Multiple PLC System Parameters (Multiple PLC Settings, Control PLC Settings) This section explains the procedures for setting up the multiple PLC system parameters with GX Developer. Refer to the GX Developer's operation manual for details on setting up all other parameters.
Page 386: Creating New Systems
19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q 19.2.2 Creating new systems Start GX Developer started up Refer to GX Developer operating manual PC parameter window on the Refer to GX Developer operating manual GX Developer opened Select "Multiple PLC Settings" to display the multiple PLC setup window.
Page 387 19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q Setting the operating mode (optional) • Selects whether to halt operations for all PLCs or continue with operations when a stop error occurs. Default: Stop all PLCs upon a stopping error at PLC No.2, No.3 or No.4.
Page 388 19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q Selects "CPU (Empty)" for the slots on which CPU modules are not to be mounted by type. Select "Detailed Settings" on the I/O assignment window to display the detail settings window. Control PLC settings (required item) •...
Page 389: Using Existing Preset Multiple Plc Settings And I/O Allocations
19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q 19.2.3 Using existing preset multiple PLC settings and I/O allocations Start Refer to the GX Developer's operation manual GX Developer started up Opens the GX Developer's PC parameter setup window. Select "Multiple PLC settings" to display the multiple PLC setup window.
Page 390 19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q The multiple PLC settings and I/O Assignment Setting data are read and written into the specified project when "OK" is selected. Confirming the multiple PLC settings When changing the CPU devices in the "Refresh settings", enter the device number after it has been changed.
Page 391 19 STARTING UP THE MULTIPLE PLC SYSTEM MELSEC-Q Setup of parameters other than the multiple PLC system settings. Set parameters written onto the hard disk or floppy disk. 19 - 9 19 - 9...
Page 392: Appendices
APPENDICES MELSEC-Q APPENDICES APPENDIX 1 Special Relay List Special relays, SM, are internal relays whose applications are fixed in the PLC. For this reason, they cannot be used by sequence programs in the same way as the normal internal relays. However, they can be turned ON or OFF as needed in order to control the CPU module and remote I/O modules.
Page 393 APPENDICES MELSEC-Q Special Relay List (1) Diagnostic Information Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) • ON if diagnosis results show error occurrence (Includes when an annunciator is ON, and when an error OFF: No error Diagnostic errors is detected with CHK instruction) S (Error)
Page 394 APPENDICES MELSEC-Q Special Relay List (2) System information Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) LED OFF • When this relay goes from OFF to ON, the LEDs SM202 ON : LED OFF command corresponding to the individual bits at SD202 go off S (Status SM203 STOP contact STOP status...
Page 395 APPENDICES MELSEC-Q Special Relay List (Continued) Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) Max. loaded I/O OFF: Ignored • When this relay goes from OFF to ON, maximum loaded SM250 +Rem read ON : Read I/O number is read to SD250. •...
Page 396 APPENDICES MELSEC-Q Special Relay List (Continued) Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) • Initial value is set at ON or OFF depending on parameters. • When this relay is OFF, all execution status are cleared from time SFC program was stopped;...
Page 397 APPENDICES MELSEC-Q Special Relay List (3) System clocks/counters Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) SM400 Always ON • Normally is ON M9036 (Every END processing) SM401 Always OFF • Normally is OFF (Every END M9037 processing) •...
Page 398 APPENDICES MELSEC-Q Special Relay List (4) Scan information Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) Low speed OFF: Completed or not • Goes ON when low speed execution type program is SM510 program executed (Every END executed.
Page 399 APPENDICES MELSEC-Q Special Relay List (Continued) Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) • Goes ON when access is made outside the range of file Q2A (S1) Memory card B OFF: Within access range registers, R. of memory card B. SM673 file register ON : Outside access range...
Page 400 APPENDICES MELSEC-Q Special Relay List (Continued) Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) PKEY instruction OFF: Instruction not • ON when PKEY instruction is being executed. SM736 execution in executed Goes OFF when CR is input, or when input character (Instruction progress flag ON : Instruction execution...
Page 401 APPENDICES MELSEC-Q Special Relay List (Continued) Corresponding Set by Applicable Number Name Meaning Explanation ACPU (When Set) Status latch OFF: Not ready S (Status SM806 • Goes ON when status latch is ready preparation ON : Ready change) Status latch SM807 ON: Latch •...
Page 402 APPENDICES MELSEC-Q (9) A to Q/QnA conversion correspondences Special relays SM1000 to SM1255 are the relays which correspond to ACPU special relays M9000 to M9255 after A to Q/QnA conversion. All of these special relays are controlled by the system so that users cannot turn them ON/OFF in the program.
Page 403 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification • Turned on when battery voltage reduces to less than OFF: Normal M9006 SM1006 Battery low specified. Turned off when battery voltage becomes ON : Battery low normal.
Page 404 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification • Used as dummy contacts of initialization and application M9036 SM1036 Always ON instruction in sequence program. • SM1038 and SM1037 are turned on and off without M9037 SM1037 Always OFF...
Page 405 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification • Provides P, I set request after transfer of the other OFF: Other than when P, I set Sub program 3 P, program (for example subprogram when main program is M9061 SM1061...
Page 406 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification • Set when consecutive transfer is not executed with Continuous OFF: When transition is consecutive transfer enabled. Reset when transfer of one M9104 SM1104 SM324...
Page 407 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification ZNRD instruction • Depends on whether or not the ZNRD (word device (LRDP instruction read) instruction has been received. OFF: Not accepted •...
Page 408 APPENDICES MELSEC-Q Special Relay List (Continued) ACPU Special Special Applicable Special Relay after Relay for Name Meaning Details Relay Conversion Modification Local station OFF: No errors Depends on whether or not a local station has detected an M9233 SM1233 error detect ON : Error detection error in another station.
Page 409 APPENDICES MELSEC-Q Special Relay List (10) For redundant systems (Host system CPU information 1) for Q4AR only SM1510 to SM1599 are only valid for redundant systems. All off for standalone systems. Set by ACPU Applicable Number Name Meaning Explanation (When Set) OFF: No-hold •...
Page 410 APPENDICES MELSEC-Q Special Relay List (Continued) Set by ACPU Applicable Number Name Meaning Explanation (When Set) SM1546 SM1546 Block 27 SM1547 SM1547 Block 28 SM1548 SM1548 Block 29 SM1549 SM1549 Block 30 SM1550 SM1550 Block 31 SM1551 SM1551 Block 32 SM1552 SM1552 Block 33 SM1553...
Page 411 APPENDICES MELSEC-Q Special Relay List (11) For redundant system (Other system CPU information 1) for Q4AR onlySM1600 to SM1650 only valid for the CPU redundant system backup mode, so they cannot be refreshed during the separate mode.Either the backup mode or the separate mode is valid for the SM4651 to SM1699.
Page 412 APPENDICES MELSEC-Q Special Relay List (Continued) Set by ACPU Applicable Number Name Meaning Explanation (When Set) SM1734 SM1734 Block 23 SM1735 SM1735 Block 24 SM1736 SM1736 Block 25 SM1737 SM1737 Block 26 SM1738 SM1738 Block 27 SM1739 SM1739 Block 28 SM1740 SM1740 Block 29 SM1741...
Page 413 APPENDICES MELSEC-Q APPENDIX 2 Special Register The special registers, SD, are internal registers with fixed applications in the PLC. For this reason, it is not possible to use these registers in sequence programs in the same way that normal registers are used. However, data can be written as needed in order to control the CPU modules and remote I/O modules.
Page 414 APPENDICES MELSEC-Q Special Register List (1) Diagnostic Information Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) Diagnostic Diagnosis • Error codes for errors found by diagnosis are stored as BIN data. D9008 format S (Error) errors error code •...
Page 415 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) • Common information corresponding to the error codes (SD0) is stored here. • The following four types of information are stored here: Slot No. Meaning Number Slot No./PLC No./Base No.
Page 416 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) Time (value set) Meaning Number Time : 1 µs units (0 to 999 µs) Time : 1 ms units (0 to 65535 ms) SD10 SD10 SD11...
Page 417 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) • Individual information corresponding to error codes (SD0) is stored here. SD16 File name/Drive name (Example) File name= Number Meaning ABCDEFGH. IJK SD16 Drive B15 to B8 B7 to B0 SD17...
Page 418 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) Error number that • Stores error number that performs error reset SD50 Error reset +Rem performs error reset • All corresponding bits go ON when battery voltage drops. •...
Page 419 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) When F goes ON due to OUT F or SET F , the F numbers which SD64 D9125 go progressively ON from SD64 through SD79 are registered. F numbers turned OFF by RST F are deleted from SD64 to SD79, SD65 D9126...
Page 420 APPENDICES MELSEC-Q Special Register List (2) System information Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) • The switch status of the remote I/O module is stored in the following format. B4 B3 S (Always) Remote Vacant Remote I/O module switch status Always 1: STOP •...
Page 421 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) • The following bit patterns are used to store the statuses of the LEDs on the CPU: B12B11 B8 B7 B4 B3 S (Status : RUN : BOOT QCPU...
Page 422 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) • When error is generated, the LED display (flicker) is made according SD207 Priorities 1 to 4 D9038 to the error number setting priorities. D3039 format SD208 Priorities 5 to 8...
Page 423 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) SD220 • LED display ASCII data (16 characters) stored here. SD221 SD220 15th character from the right 16th character from the right SD222 SD221 13th character from the right 14th character from the right...
Page 424 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) When Xn0 of the installed CC-Link goes ON, the bit corresponding to the station switches ON. When either Xn1 or XnF of the installed CC-Link switch OFF, the bit corresponding to the station switches ON.
Page 425 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) Number of points SD302 • Stores the number of points currently set for D devices Device allocated for D allocation Number of points SD303 (Same as •...
Page 426 APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) Information from SD381 • Configuration is identical to that for the first module. 2nd module Ethernet instruction Information from SD382 • Configuration is identical to that for the first module. S (Initial) reception 3rd module...
Page 427 APPENDICES MELSEC-Q Special Register List (4) Scan information Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) Execution type of Execution • Program number of program currently being executed is S (Status SD500 program being program No. stored as BIN value. change) executed File name of low...
Page 428: Appendix 2 Special Register List
APPENDICES MELSEC-Q Special Register List (Continued) Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) • Stores wait time when constant scan time has been set. Constant scan wait SD542 (in 1 ms units) time (in 1 ms units) S (First Constant scan •...
Page 429 APPENDICES MELSEC-Q Special Register List (5) Memory card Corresponding Set by Corresponding Number Name Meaning Explanation ACPU (When set) • Indicates memory card A model installed B8 B7 B4 B3 ----------- 0< >0 Drive 1 0: Does not exist S (Initial and card QCPU (RAM) model 1: SRAM...
Page 430 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) • Indicates memory card B models installed B8 B7 B4 B3 ----------- 0< >0 Q2A (S1) Drive 1 0: Does not exist Memory card Memory card SD620 S (Initial)
Page 431 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) • Stores the comment file name (with extension) selected at the SD651 parameters or by the QCDSET instruction in ASCII code. SD652 SD651 Second character First character SD653...
Page 432 APPENDICES MELSEC-Q Special Register List (Continued) Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) SD738 • Stores the message designated by the MSG instruction. SD739 SD740 SD738 2nd character 1st character SD739 4th character SD741 3rd character SD740 6th character 5th character...
Page 433 APPENDICES MELSEC-Q Special Register List (7) Debug Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) Remaining No. of simultaneous • Stores the remaining number of simultaneous execution of the CC- SD780 execution of 0 to 32 Link dedicated instructions. CC-Link dedicated instruction...
Page 434 APPENDICES MELSEC-Q Special Register List (8) Latch area Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) Access file Drive where drive number S (Status SD900 power was • Stores drive number if file was being accessed during power loss. change) during power interrupted...
Page 435 APPENDICES MELSEC-Q (9) A to Q/QnA conversion correspondences ACPU special registers D9000 to D9255 correspond to the special registers SD1000 to SD1255 after A-series to the Q/QnA-series conversion. These special registers are all set by the system, and users cannot use them to set program data.
Page 436 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • If I/O modules, of which data are different from data entered, are detected when the power is turned on, the first I/O number of the lowest number unit among the detected units is stored in hexadecimal.
Page 437 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • When operation error has occurred during execution of application instruction, the step number, at which Step number at the error has occurred, is stored in BIN code.
Page 438 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • If scan time is larger than the content of SD526, the Maximum scan value is newly stored at each END. Namely, the D9019 SD1019 SD526...
Page 439 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • Turned on/off with a peripheral device. For sampling Step or time during At scanning----------0 D9044 SD1044 trace sampling trace At time ----------------Time (10 msec unit) Stores the value in BIN code.
Page 440 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • Sets the time check time of the data link instructions (ZNRD, ZNWR) for the MELSECNET/10. Register for • Setting range: 1 s to 65535 s (1 to 65535) D9085 SD1085...
Page 441 APPENDICES MELSEC-Q Special Register List (Continued) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • When one of F0 to 255 (F0 to 2047 for AuA and AnU) is turned on by SET F 1 is added to the contents of SD63.
Page 442 APPENDICES MELSEC-Q Special Register List (10) Special register list dedicated for QnA ACPU Special Special Corresponding Name Meaning Details Special Register after Register for Conversion Conversion Modification Stores the execution result of the ZNRD (word device read) instruction 0: Normal end •...
Page 443 APPENDICES MELSEC-Q Special Register List (Continue) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification • Loopback in forward/reverse loops Master station 0: Forward loop, Station 2 Station 3 Station 1 Station n during data link 1: Reverse loop, during data link Forward loopback...
Page 444 APPENDICES MELSEC-Q Special Register List (Continue) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification Stores conditions Stores the local station numbers which are in D9216 SD1216 for up to numbers error. 1 to 16 Device number Stores conditions...
Page 445 APPENDICES MELSEC-Q Special Register List (Continue) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification Stores conditions Stores the local or remote station number at which a D9232 SD1232 for up to numbers forward or reverse loop error has occurred 1 to 8 Device Stores conditions...
Page 446 APPENDICES MELSEC-Q Special Register List (Continue) ACPU Special Special Corresponding Special Register after Register for Name Meaning Details Conversion Conversion Modification Stores conditions Stores the local station number which is in STOP or PAUSE D9248 SD1248 for up to numbers 1 mode.
Page 447 APPENDICES MELSEC-Q Special Register List (Continue) (12) I/O module verification Set by Corresponding Corresponding Number Name Meaning Explanation (When ACPU set) SD1400 • When the power is turned on, the module numbers of the I/O D9116 modules whose information differs from the registered I/O module SD1401 D9117 information are set in this register (in units of 16 points).
Page 448 APPENDICES MELSEC-Q Special Register List (Continue) (14) For redundant systems (Other system CPU information 1) for Q4AR only SD1600 to SD1659 is only valid during the back up mode for redundant systems, and refresh cannot be done when in the separate mode. When a standalone system SD1600 to SD1699 are all 0.
Page 449: Appendix 3 List Of Interrupt Pointer Nos. & Interrupt Factors
APPENDICES MELSEC-Q APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors Priority Priority I No. Interrupt Factors I No. Interrupt factors Ranking Ranking 1st point Errors that stop operation 2nd point Empty —— 3rd point UNIT VERIFY ERR. 4th point FUSE BREAK OFF SP.
Page 450 APPENDICES MELSEC-Q MEMO App - 59 App - 59...
Page 451 INDEX Duty ..............10-25 Accuracy of initial scan time...... 4-16 DX (Direct access input)......10- 6 Accuracy of scan time ....... 4-18 DY (Direct access output)......10- 9 Annunciator (F) ........10-12 ASCII code..........4-51 ATA card ............ 6-11 E (Real numbers).........10-62 Auto mode ..........5- 3 Edge relay(V) ..........10-16 Automatic write to standard ROM.....
Page 452 High speed timer (T) ........10-20 M (Internal relay)..........10-10 Macro instruction argument device (VD)..10-60 I (Interrupt pointer)........10-56 Main routine program........4- 3 I/O No. designation device (Un)....10-59 Memory card ..........6-11 Index register (Z) ......... 10-39 Monitor condition setting........7-25 Initial execution monitor time ......4-16 Monitoring the local devices ......7-30 Initial execution type program.......
Page 453 Refresh mode..........4-38 ST (Retentive timer: OUT ST ) ....10-21 Refresh output..........10- 9 Stand-by type program ........4-25 Remote latch clear ........7-19 Standard RAM ..........6- 9 Remote operation.......... 7-12 Standard RAM memory capacity ....6- 9 Remote PAUSE..........7-15 Standard ROM ..........6- 8 Remote password ........7- 1, 7-67 Step relay (S) ..........10-18 Remote RESET..........
Page 454 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the dealer or Mitsubishi Service Company.
Page 455 Microsoft Windows, Microsoft Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium is a registered trademark of Intel Corporation in the United States and other countries. Ethernet is a registered trademark of Xerox. Co., Ltd in the United States. Other company and product names herein are either trademarks or registered trademarks of their respective owners.
Page 456 High Performance Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals) QCPU(Q)-U(KI)-E MODEL MODEL 13JL98 CODE SH(NA)-080038-D(0204)MEE HEAD OFFICE : 1-8-12, OFFICE TOWER Z 14F HARUMI CHUO-KU 104-6212,JAPAN NAGOYA WORKS : 1-14 , YADA-MINAMI 5 , HIGASHI-KU, NAGOYA , JAPAN When exported from Japan, this manual does not require application to the Ministry of Economy, Trade and Industry for service transaction permission.

Mitsubishi QCPU (Q Mode) User Manual

1 Overview

2 System Configuration for Single Cpu System

3 Performance Specification

4 Sequence Program Configuration and Execution Conditions

5 Assignment of I/O Numbers

6 High Performance Model Qcpu Files

7 Function

8 Communication with Intelligent Function Module/Special Function Module

9 Parameter List

10 Devices

11 High Performance Model Qcpu Processing Time

12 PROCEDURE for WRITING PROGRAMS to HIGH PERFORMANCE MODEL QCPU 12- 1 To-12

13 Outline of Multiple Plc Systems

14 System Configuration of Multiple Plc Systems

15 Allocating Multiple Plc System I/O Numbers

16 Communication between Cpu Modules in Multiple Plc System

17 Communications between the Multiple Plc System's I/Omodules and Intelligent Function Modules

18 PROCESSING TIME for MULTIPLE PLC SYSTEM HIGH PERFORMANCE MODEL Qcpus

19 Starting up the Multiple Plc System

APPENDIX 1 Special Relay List

APPENDIX 2 Special Register List

APPENDIX 3 List of Interrupt Pointer Nos. & Interrupt Factors

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