Integra DTR-7.8 Service Manual page 188

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -86
Q1002: IS25C02(2 kbit EEPROM)
BLOCK DIAGRAM
TE
L 13942296513
PIN CONFIGURATION
TERMINAL DESCRIPTION
www
.
http://www.xiaoyu163.com
STATUS
REGISTER
DATA
REGISTER
SI
MODE
DECODE
CS
LOGIC
WP
CLOCK
SCK
HOLD
CS 1
SO 2
WP 3
GND 4
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
x ao u163
y
V Power
CC
i
WP Write Protect
HOLD Suspends Serial Input
http://www.xiaoyu163.com
2 9
8
VCC
256 x 8/512 x 8
MEMORY ARRAY
ADDRESS
DECODER
Q Q
3 6 7 1 3 1 5
8 VCC
7 HOLD
6 SCK
5 SI
co
.
9 4 2 8
GND
OUTPUT
BUFFER
SO
0 5 8 2 9 9 4 2 8
m
DTR-7.8
9 9
9 9