Integra DTR-7.8 Service Manual page 170

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -68
Q8501: SII9135CTU (HDMI RECEIVER)
TERMINAL DESCRIPTION(2/4)
Digital Audio Output Pins
Pin Name
XTALIN
XTALOUT
MCLK
SCK/DCLK
WS/DR0
SD0/DL0
SD1/DR1
SD2/DL1
SD3/DR2
SPDIF/DL2
TE
L 13942296513
MUTEOUT
Differential Signal Data Pins
Pin Name
R0XC+
R0XC-
R0X0+
R0X0-
R0X1+
R0X1-
R0X2+
R0X2-
R1XC+
R1XC-
R1X0+
R1X0-
www
R1X1+
R1X1-
R1X2+
.
R1X2-
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Pin # Strength Type
95 ---
Tolerant
LVTTL
94 4 mA LVTTL
LVTTL
89 8 mA
LVTTL
86 4 mA
LVTTL
85 4 mA
LVTTL
81 4 mA
LVTTL
82 4 mA
LVTTL
83 4 mA
LVTTL
84 4 mA
LVTTL
78 4 mA
LVTTL
75 4 mA
Type
Pin #
Analog
40
39 Analog
Analog
44
Analog
43
Analog
48
Analog
47
Analog
52
Analog
51
Analog
58
Analog
57
Analog
62
Analog
61
Analog
66
Analog
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y
Analog
70
i
Analog
69
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2 9
8
Dir
5V In
Crystal Clock Input. Also allows LVTTL input.
Frequency required: 26-28.5 MHz
Out
Crystal Clock Output
Out Audio Master Clock Output
Out
I2S Serial Clock Output.
DSD Clock Out.
Out
I2S Word Select Output.
DSD Serial Right Ch0 Data Output
Out
I2S Serial Data Output / DSD Audio Output
Configurable to be shared with DSD.
Out
SD0 = DSD Serial Left Ch0 Data Output
Out
SD1 = DSD Serial Right Ch1 Data Output
Out
SD2 = DSD Serial Left Ch1 Data Output
Out
S/PDIF Audio Output. Configurable to be
shared with DSD
Q Q
3 6 7 1 3
DSD Serial Left Ch2 Data Output
Out
Mute Audio Output. Signal to the external
downstream audio device, audio DAC, etc. to
downstream audio device, audio DAC, etc. to
mute audio output.
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
.
9 4 2 8
Description
1 5 0 5 8 2 9 9 4
Description
HDMI Port 0
HDMI Port 1
m
co
DTR-7.8
9 9
2 8 9 9