Integra DTR-7.8 Service Manual page 143

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -41
Q3661:M12L64164A-7TG (64 Mbit Syncronous DRAM)
BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
CS
RAS
CAS
WE
PIN CONFIGURATION
TE
L 13942296513
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Mode
Register
Top View
1 54
V
DD
2 53
DQ 0
3 52
V
D D Q
4 51
DQ 1
5 50
DQ 2
6 49
V
S S Q
7 48
DQ 3
8 47
DQ 4
46
V 9
D D Q
10 45
DQ 5
11 44
DQ 6
43
V 12
S S Q
42
DQ 7 13
41
V 14
DD
40
L DQ M 15
39
W E 16
38
C AS 17
37
R AS 18
36
CS 19
35
A 20
13
34
A 21
12
33
A /AP 22
10
32
A 23
0
31
A 24
1
30
A 25
2
29
x A 26 ao
3
y
28
V 27
DD
i
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8
Row
Address
Buffer
Bank A
&
Refresh
Counter
Sense Amplifier
Column
Column Decoder
Address
Buffer
&
Refresh
Counter
Data Control Circuit
Q Q
3 6 7 1 3
FEATURES
JEDEC standard 3.3V power supply
V
SS
LVTTL compatible with multiplexed address
DQ15
Four banks operation
V
S S Q
MRS cycle with address key programs
DQ14
- CAS Latency (2 & 3)
DQ13
- Burst Length (1, 2, 4, 8 & full page)
V
D D Q
- Burst Type (Sequential & Interleave)
DQ12
All inputs are sampled at the positive going edge
DQ11
of the system clock
V
S S Q
Auto & self refresh
DQ10
15.6 us refresh interval
DQ 9
V
D D Q
DQ 8
V
S S
N C
U D Q M
CLK
CKE
N C
A
11
A
9
A
8
A
7
A
6
A
5
u163 A
4
V
S S
.
2 9 9 4 2 8
Bank D
Bank C
Bank B
1 5 0 5 8 2 9 9 4
m
co
DTR-7.8
9 9
L(U)DQM
DQ
2 8 9 9