Integra DTR-7.8 Service Manual page 160

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -58
Q8210, Q8510, Q8610: BR24L02FV-W(256x8 bit EEPROM)
BLOCK DIAGRAM AND PIN CONFIGURATION
A0 1
A1 2
A2 3
4
GND
TE
L 13942296513
TERMINAL DESCRIPTION
Terminal
A0,A1,A2
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2k Bit EEPROM Array
8bit
Address
Slave word
8bit
Decorder address register
START
Control circuit
High-voltage
Power voltage
generation circuit
detection
I/O
Vcc - Apply a power source
GND - Ground terminal
I Slave address setting terminal
SCL I Serial clock input
Slave and word address.
I/O
SDA
Serial data input and output
WP I Write protect terminal
x ao
y
i
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8
8bit
Data
register
STOP
ACK
Q Q
3 6 7 1 3
Function
u163
.
2 9 9 4 2 8
8
Vcc
7 WP
6
SCL
5 SDA
1 5 0 5 8 2 9 9 4
m
co
DTR-7.8
9 9
2 8 9 9