Integra DTR-7.8 Service Manual page 140

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -38
Q7391: IS25C64A(64 kbit EEPROM)
BLOCK DIAGRAM
SI
CS
WP
SCK
TE
L 13942296513
PIN CONFIGURATION
TERMINAL DESCRIPTION
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.
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STATUS
REGISTER
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
HOLD
CS 1
2
SO
NC 3
NC 4
5
NC
WP 6
GND 7
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
V Power
CC
x ao u163
y
WP Write Protect
i
HOLD Suspends Serial Input
NC No Connect
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2 9
8
VCC
8192 x 8/4096 x 8
MEMORY ARRAY
ADDRESS
DECODER
Q Q
3 6 7 1 3 1 5
14 VCC
13
HOLD
12 NC
11 NC
10
NC
9 SCK
8 SI
co
.
9 4 2 8
GND
OUTPUT
BUFFER
so
0 5 8 2 9 9 4 2 8
m
DTR-7.8
9 9
9 9