Integra DTR-7.8 Service Manual page 173

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -71
Q8011: SST25VF080B (8 Mbit Serial Flash Memory)
BLOCK DIAGRAM
TE
L 13942296513
PIN CONFIGURATION
TERMINAL DESCRIPTION
Symbol Pin Name
SCK Serial Clock
SI Serial Data
Input
SO Serial Data
Output
CE# Chip Enable
www
WP# Write Protect
HOLD# Hold
.
V Power Supply
DD
V Ground
SS
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Address
Buffers
and
Latches
Control Logic
CE# SCK
CE#
1
SO
2
WP#
3
V SS
4
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
x ao u163
y
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
i
To provide power supply voltage: 2.7-3.6V for SST25VF080
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2 9
8
SuperFlash
X - Decoder
Memory
Y - Decoder
I/O Buffers
Data Latches
Serial Interface
SI SO WP# HOLD#
Q Q
3 6 7 1 3 1 5
V DD
8
HOLD#
7
Top View
SCK
6
SI
5
co
.
9 4 2 8
and
0 5 8 2 9 9 4 2 8
m
DTR-7.8
9 9
9 9