Integra DTR-7.8 Service Manual page 155

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -53
Q8101 : AD8196 (HDMI/DVI Switch with Equalization)
BLOCK DIAGRAM
I2C_SDA
I2C_SCL
I2C_ADDR
IP_A[3:0]
IN_A[3:0]
IP_B[3:0]
IN_B[3:0]
AUX_A[3:0]
AUX_B[3:0]
TE
L 13942296513
PIN CONFIGURATION
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SERIAL INTERFACE
CONFIG
INTERFACE
VTTI
+
4
4
–
+
4 EQ
4
–
HIGH SPEED
VTTI
4
4
LOW SPEED
AVCC 1
IN_A0 2
IP_A0 3
AVEE 4
IN_A1 5
IP_A1 6
VTTI 7
TOP VIEW
IN_A2 8
(Not to Scale)
IP_A2 9
AVCC 10
IN_A3 11
IP_A3 12
AVEE 13
I2C_ADDR 14
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8
RESET
AD8196
CONTROL
LOGIC
4
SWITCH
CORE
PE
BUFFERED
SWITCH
CORE
Q Q
3 6 7 1 3
UNBUFFRED
BIDIRECTIONAL
42 AVCC
41 IP_B3
40 IN_B3
39 AVEE
38 IP_B2
37 IN_B2
AD8196
36 VTTI
35 IP_B1
34 IN_B1
33 AVCC
32 IP_B0
31 IN_B0
30 AVEE
29 I2C_SDA
.
2 9 9 4 2 8
AVCC
DVCC
AMUXVCC
AVEE
DVEE
VTTO
+
OP[3:0]
ON[3:0]
4
–
4
AUX_COM[3:0]
1 5 0 5 8 2 9 9 4
m
co
DTR-7.8
9 9
2 8 9 9