Integra DTR-7.8 Service Manual page 131

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -29
Q3601 : D707E001BRFP250 (32 bit Floating-Point Digital Signal Processor)
TERMINAL DESCRIPTION(1/3)
SIGNAL NAME
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
EM_CAS
EM_RAS
TE
L 13942296513
EM_WE
EM_CKE
EM_CLK
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_OE
EM_RW
EM_D[0]
EM_D[1]
EM_D[2]
EM_D[3]
EM_D[4]
EM_D[5]
EM_D[6]
EM_D[7]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
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EM_D[14]
EM_D[15]
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PIN NO. TYPE DESCRIPTION
External Memory Interface (EMIF) Addressand Control
91 O
89 O
88 O
86 O
84 O
83 O
EMIF Address Bus
80 O
79 O
76 O
75 O
93 O
74 O
96 O
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
94 O
97 O SDRAM Chip Select
100 O Asynchronous Memory Chip Select
37 O SDRAM Column Address Strobe
98 O SDRAM Row Address Strobe
38 O SDRAM Write Enable
71 O SDRAM Clock Enable
70 O SDRAM Clock
39 O Write Enable or Byte Enable for EM_D[7:0]
67 O Write Enable or Byte Enable for EM_D[15:8]
104 O SDRAM Output Enable
102 O Asynchronous Memory Read/not Write
External Memory Interface (EMIF) Data Bus
52 IO
51 IO
49 IO
48 IO
46 IO
45 IO
43 IO
41 IO
EMIF Data Bus [Lower 16 Bits]
66 IO
64 IO
63 IO
61 IO
59 IO
58 IO
56 IO
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55 IO
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