Integra DTR-7.8 Service Manual page 169

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -67
Q8501: SII9135CTU (HDMI RECEIVER)
TERMINAL DESCRIPTION(1/4)
Video and Audio Pins
Pin Name
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
TE
L 13942296513
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
DE
www
HSYNC
VSYNC
.
EVNODD
ODCK
http://www.xiaoyu163.com
Pin # Strength
16 8 mA
15
14
13
10
9
8
7
3
2
1
144
141
140
139
138
135
134
133
132
129
128
127
126
123
122
121
120
117
116
115
114
111
110
109
108
19 8 mA
20 8 mA
x ao u163
y
21 8 mA
i
22 8 mA
12 mA
5
http://www.xiaoyu163.com
2 9
8
Type Dir
LVTTL Output
36-Bit Output Pixel Data Bus. Q35:0
is highly configurable using the
Output
LVTTL
VDD_CONFIG register. It supports a
Output
LVTTL
wide array of output formats, including
Output
LVTTL
multiple RBG and YCbCr bus formats.
Output
LVTTL
Using the appropriate bits in the PD
Output register, the output drivers can be put
LVTTL
into a high impedance (tri-state)
Output
LVTTL
mode. A weak, internal pull-down
Output
LVTTL
device brings each output to ground.
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
LVTTL Output
Output
LVTTL
LVTTL Output
Q Q Output
LVTTL
3 6 7 1 3 1 5
LVTTL Output
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
Output
LVTTL
LVTTL Output
Output
LVTTL
LVTTL Output
Output
LVTTL
Output
LVTTL
Data Enable
Output
LVTTL
Horizontal Sync Output
co
Output
LVTTL
Vertical Sync Output
.
Output
LVTTL Indicates Even or Odd Field for
Interlaced Formats
LVTTL Output
Output Data Clock
9 4 2 8
Description
0 5 8 2 9 9 4 2 8
m
DTR-7.8
9 9
9 9