Integra DTR-7.8 Service Manual page 129

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -27
Q3601 : D707E001BRFP250 (32 bit Floating-Point Digital Signal Processor)
BLOCK DIAGRAM
C67x+ CPU
I/O INT
I/O Interrupts
TE
L 13942296513
Out
SYSTEM DIAGRAM
C67x+
DSP Core
Program
Cache
EMIF
www
.
http://www.xiaoyu163.com
D1
Data 64
R/W
D2
Memory
Data 64
Controller
R/W
Program
Fetch
CSP
Program
Cache 256
PMP DMP
32K Bytes
32 32
High-Performance
Crossbar Switch
32 32 32
MAX0 CONTROL MAX1
dMAX
DSP
192K
Bytes
RAM
768K
Bytes
ROM
Crossbar Switch
dMAX
PLL
ASYNC
FLASH
x ao
y
Host
Microprocessor
i
100 MHz
SDRAM
http://www.xiaoyu163.com
8
Program/Data
JTAG EMU
192 RAM
192K Bytes
Program/Data
256 ROM Page1
256K Bytes
Program/Data
256 ROM Page2
256K Bytes
Program/Data
256 ROM Page3
256K Bytes
32 32
32
32
Events
Q Q
3 6 7 1 3
In
EMIF
Audio Zone 1
McASP0
SPI or I2C
SPI1
Control (optional)
I2C0
Audio Zone 2
McASP1
Audio Zone 3
McASP2
SPIO
I2C1
RTI
OSC
DSP Control
SPI or I2C
u163
.
2 9 9 4 2 8
McASP0
32
16 Serializers
32
32
McASP1
6 Serializers
32
32 McASP2
2 Serializers
32
DIT Only
32 SPI1
32 SPI0
32 I2C0
32 I2C1
32 RTI
32 PLL
1 5 0 5 8 2 9 9 4
CODEC, DIR,
ADC, DAC, DSD,
Network
CODEC, DIR,
ADC, DAC, DSD,
Network
Digital Out
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins
m
co
DTR-7.8
9 9
2 8 9 9