Integra DTR-7.8 Service Manual page 126

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -24
Q3501: D788E001BRFP266/D708E001BRFP266 (Audio DSP)
TERMINAL DESCRIPTION(1/3)
SIGNAL NAME
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
TE
L 13942296513
EM_CAS
EM_RAS
EM_WE
EM_CKE
EM_CLK
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_OE
EM_RW
(1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are
separated with a slash (/).
(2) PULL column:
IPD = Internal Pulldown resistor
IPU = Internal Pullup resistor
(3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise marked.
www
.
http://www.xiaoyu163.com
PIN
(1)
TYPE PULL
NO.
External Memory Interface (EMIF) Address and Control
91 O
89 O
88 O
86 O
84 O
83 O
80 O
79 O
76 O
75 O
93 O
74 O
96 O
94 O
97 O
100 O
37 O
98 O
38 O
71 O
70 O
39 O
67 O
104 O
102 O
x ao u163
y
i
http://www.xiaoyu163.com
2 9
8
(2) (3)
GPIO
- N
- N
- N
- N
- N
- N
EMIF Address Bus
- N
- N
- N
- N
- N
- N
- N
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
- N
- N SDRAM Chip Select
- N Asynchronous Memory Chip Select
Q Q
3 6 7 1 3 1 5
- N SDRAM Column Address Strobe
- N SDRAM Row Address Strobe
- N SDRAM Write Enable
- N SDRAM Clock Enable
- N SDRAM Clock
- N Write Enable or Byte Enable for EM_D[7:0]
- N Write Enable or Byte Enable for EM_D[15:8]
- N SDRAM Output Enable
- N Asynchronous Memory Read/not Write
co
.
9 4 2 8
DESCRIPTION
0 5 8 2 9 9 4 2 8
m
DTR-7.8
9 9
9 9