Integra DTR-7.8 Service Manual page 158

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -56
Q8801: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
TERMINAL DESCRIPTION
Mnemonic
P7–P0
CLOCK
HSYNC
FIELD/VSYNC
BLANK
SCRESET/RTC
V
REF
R
SET1
R
SET2
COMP1
TE
L 13942296513
COMP2
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
SCLOCK
SDATA
CLAMP
PAL_NTSC
VSO
CSO_HSO
ALSB
RESET
TTX
TTXREQ
V
AA
GND
www
.
http://www.xiaoyu163.com
Input/Output
I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7ÐP0) P0 represents the LSB.
I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alter-
natively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
I/O HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or as an input and accept (Slave Mode) Sync signals.
I/O Dual Function FIELD (Mode 1) and
configured to output (Master Mode) or as an input (Slave Mode) and accept these
control signals.
I/O Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0."
This signal is optional.
I T his pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It
can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a Real-
Time Control (RTC) Input.
I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
I A 150 resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs A, B, and C (the "large" DACs).
I A 600 resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs D, E, and F (the "small" DACs).
O Compensation Pin for DACs A, B, and C. Connect a 0.1 uF Capacitor from COMP to
V . For Optimum Dynamic Performance in Low Power Mode, the value of the
AA
COMP1 capacitor can be lowered to as low as 2.2 nF.
O Compensation Pin for DACs D, E, and F. Co nnect a 0.1 uF Capacitor from COMP to V
O GREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.
O BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.
O RED/S-Video C /V Analog Output. This DAC is capable of providing 34.66 mA output.
O GREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.
O BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.
O RED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.
I MPU Port Serial Interface Clock Input.
I/O MPU Port Serial Data Input/Output.
O TTL Output Signal to external circuitry to enable clamping of all video signals.
I Input signal to select PAL or NTSC mode of operation, pin set to Logic "1" selects PAL.
O VSO TTL Output Sync Signal.
O D ual Function CSO or HSO TTL Output Sync Signal.
I TTL Address Input. This signal sets up the LSB of the MPU address.
I T he input resets the on-chip timing generator and sets the ADV7172/ADV7173 into
default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered
OFF, DACs D, E, and F powered ON, Composite and S-Video out.
I T eletext Data Input Pin.
O T eletext Data Request output signal used to control teletext data transfer.
Power Supply (3 V to 5 V).
I
G Ground Pin.
x ao
y
i
http://www.xiaoyu163.com
8
Function
VSYNC
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
(Mode 2) Control Signal. This pin may be
1 5 0 5 8 2 9 9 4
m
co
DTR-7.8
9 9
2 8 9 9
.
AA