Integra DTR-7.8 Service Manual page 135

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -33
Q3451: ES29LV160ET-70TG (16 Mbit Flash Memory)
TERMINAL DESCRIPTION
A0-A19
DQ0-DQ14
DQ15/A-1
RESET#
BYTE#
RY/BY#
TE
L 13942296513
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Pin
20 Addresses
15 Data Inputs/Outputs
DQ15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
CE# Chip Enable
OE# Output Enable
WE# Write Enable
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit mode
Ready/Busy Output (N/A SO 044)
3.0 volt-only single power supply
Vcc
(see Product Selector Guide for speed options and voltage supply tolerances)
Vss Device Ground
NC Pin Not Connected Internally
LOGIC SYMBOL
20
A0 ~ A19
CE#
OE#
WE#
RESET#
BYTE#
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y
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8
Description
Q Q
3 6 7 1 3
16 or 8
DQ0 ~ DQ15
(A-1)
RY/BY#
(N/A SO 044)
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2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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co
DTR-7.8
9 9
2 8 9 9