Integra DTR-7.8 Service Manual page 120

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -18
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Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP)
TERMINAL DESCRIPTION(2/5)
SIGNAL NAME
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
EM_CAS
TE
L 13942296513
EM_RAS
EM_WE
EM_CKE
EM_CLK
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_WE_DQM[2]
EM_WE_DQM[3]
EM_OE
EM_RW
EM_WAIT
(1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are
separated with a slash (/).
(2) PULL column:
IPD = Internal Pulldown resistor
IPU = Internal Pullup resistor
(3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise marked.
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BALL
(1)
TYPE PULL
NO.
External Memory Interface (EMIF) Address and Control
J16 O
J15 O
K15 O
L16 O
L15 O
M16 O
M15 O
N16 O
N15 O
P16 O
H15 O
P15 O
P12 O
G15 O
H16 O
F15 O
E15 O
R3 O
F16 O
T3 O
T14 O
R14 O
R4 O
T13 O
P13 O
R15 O
D15 O
E16 O
D14 I
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8
(2) (3)
GPIO
- N
- N
- N
- N
- N
- N
- N EMIF Address Bus
- N
- N
- N
- N
- N
IPD N
- N
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
- N
- N SDRAM Chip Select
- N Asynchronous Memory Chip Select
Q Q
- N SDRAM Column Address Strobe
3 6 7 1 3
- N SDRAM Row Address Strobe
- N SDRAM Write Enable
- N SDRAM Clock Enable
- N SDRAM Clock
- N Write Enable or Byte Enable for EM_D[7:0]
- N Write Enable or Byte Enable for EM_D[15:8]
IPU N Write Enable or Byte Enable for EM_D[23:16]
IPU N Write Enable or Byte Enable for EM_D[31:24]
- N SDRAM Output Enable
- N Asynchronous Memory Read/not Write
Asynchronous Wait Input (Programmable Polarity) or
IPU N
Interrupt (NAND)
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DESCRIPTION
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DTR-7.8
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