Integra DTR-7.8 Service Manual page 152
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Also See for DTR-7.8:
- Instruction manual (128 pages) ,
- Instruction manual (128 pages) ,
- Service manual (339 pages)
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -50
Q8001: FLI8125-LF-BC (Video Processor)
TERMINAL DESCRIPTION(6/8)
LVDS Display Interface
Pin Name
AVSS_OUT_LV
AVDD_OUT_LV_33
TTL Display Interface
Pin Name
PBIAS
PPWR
AVDD_LV_33
VCO_LV
AVSS_LV
AVDD_OUT_LV_33
R0
R1
R2
R3
R4
R5
R6
TE
L 13942296513
R7
G0
G1
AVSS_OUT_LV
AVDD_OUT_LV_33
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
AVSS_OUT_LV
AVDD_OUT_LV_33
PD20/B4
PD21/B5
PD22/B6
PD23/B7
DEN
DHS
www
DVS
DCLK
PD24
.
PD25
PD26
PD27
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No
I/O
Description
82
G
Ground for LVDS outputs.
83
DP
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
No
I/O
Description
For 8-bit panels
53
O
Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
54
O
Panel Power Control [Tri-state output, 5V- tolerant]
56
DP
Digital Power for TTL Block. Connect to digital 3.3V supply.
57
O
Reserved. Output for Testing Purpose only at Factory.
58
G
Ground for TTL outputs.
59
DP
Digital Power for TTL outputs. Connect to digital 3.3V supply.
60
O
Red channel bit 0 (Even)
61
O
Red channel bit 1 (Even)
62
O
Red channel bit 2
63
O
Red channel bit 3
64
O
Red channel bit 4
65
O
Red channel bit 5
66
O
Red channel bit 6
67
O
Red channel bit 7
68
O
Green channel bit 0
69
O
Green channel bit 1
70
G
Ground for TTL outputs.
71
DP
Digital Power for TTL outputs. Connect to digital 3.3V supply.
72
O
Green channel bit 2
73
O
Green channel bit 3
74
O
Green channel bit 4
75
O
Green channel bit 5
76
O
Green channel bit 6
77
O
Green channel bit 7
78
O
Blue channel bit 0 (Even)
79
O
Blue channel bit 1 (Even)
80
O
Blue channel bit 2 (Even)
81
O
Blue channel bit 3 (Even)
82
G
Ground for TTL outputs.
83
DP
Digital Power for TTL outputs. Connect to digital 3.3V supply.
86
O
Blue channel bit 4 (Even)
87
O
Blue channel bit 5 (Even)
88
O
Blue channel bit 6 (Even)
89
O
Blue channel bit 7 (Even)
90
O
Display Data Enable
91
O
Display Horizontal Sync.
92
O
Display Vertical Sync.
x
ao
u163
93
O
Display Pixel Clock
y
115
O
Red channel bit 0 (Odd)
i
114
O
Red channel bit 1 (Odd)
113
O
Red channel bit 2
112
O
Red channel bit 3
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2 9
8
For 6-bit panels
Not used.
Not used.
(Even)
Red channel bit 0 (Even)
(Even)
Red channel bit 1 (Even)
(Even)
Red channel bit 2 (Even)
(Even)
Red channel bit 3 (Even)
(Even)
Red channel bit 4 (Even)
Q Q
3
6 7
1 3
1 5
(Even)
Red channel bit 5 (Even)
(Even)
Not used.
(Even)
Not used.
(Even)
Green channel bit 0 (Even)
(Even)
Green channel bit 1 (Even)
(Even)
Green channel bit 2 (Even)
(Even)
Green channel bit 3 (Even)
(Even)
Green channel bit 4 (Even)
(Even)
Green channel bit 5 (Even)
Not used.
Not used.
Blue channel bit 0 (Even)
Blue channel bit 1 (Even)
Blue channel bit 2 (Even)
Blue channel bit 3 (Even)
Blue channel bit 4 (Even)
Blue channel bit 5 (Even)
co
Not used.
.
Not used.
(Odd)
Red channel bit 0 (Odd)
(Odd)
Red channel bit 1 (Odd)
9 4
2 8
0 5
8
2 9
9 4
2 8
m
DTR-7.8
9 9
9 9
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